TerosHDL linter report

Filters: All Warnings Errors

/tests/command/linter/helpers/sample_0.vhd 6 problems (6 errors, 0 warnings)

Severity	Position	Message
Error	Row 13, Column 18	"':' is expected instead of ';'"
Error	Row 13, Column 18	"type mark expected in a subtype indication"
Error	Row 18, Column 0	"'<=' is expected instead of 'end'"
Error	Row 18, Column 0	"primary expression expected"
Error	Row 16, Column 19	"';' expected at end of signal assignment"
Error	Row 16, Column 19	"(found: 'end')"

				
			Line
			Source
		
	1
	library ieee;

	2
	use ieee.std_logic_1164.all;

	3
	
	4
	
	5
	entity XOR_ent is

	6
	port(	x: in std_logic;

	7
		y: in std_logic;

	8
		F: out std_logic

	9
	);

	10
	end XOR_ent;  

	11
	
	12
	architecture behv2 of XOR_ent is 

			Error
	
		Row 13, Column 18
	
		"':' is expected instead of ';'"
	
			Error
	
		Row 13, Column 18
	
		"type mark expected in a subtype indication"
	
	13
	    constant cnt_s;

	14
	begin 

	15
	
			Error
	
		Row 16, Column 19
	
		"';' expected at end of signal assignment"
	
			Error
	
		Row 16, Column 19
	
		"(found: 'end')"
	
	16
	    F <= x xor y; s

	17
	
			Error
	
		Row 18, Column 0
	
		"'<=' is expected instead of 'end'"
	
			Error
	
		Row 18, Column 0
	
		"primary expression expected"
	
	18
	end behv2;

	19

/tests/command/linter/helpers/sample_1.vhd 5 problems (5 errors, 0 warnings)

Severity	Position	Message
Error	Row 23, Column 18	"no declaration for "sstd_logic""
Error	Row 33, Column 44	"no declaration for "insput2""
Error	Row 34, Column 32	"can't associate 'wire' with signal interface "x""
Error	Row 34, Column 32	"(type of 'wire' is std_logic)"
Error	Row 23, Column 12	"(type of signal interface "x" is an erroneous type)"

				
			Line
			Source
		
	1
	library ieee;				

	2
	use ieee.std_logic_1164.all;

	3
	use work.all;

	4
	
	5
	entity comb_ckt is

	6
	port(	input1: in std_logic;

	7
		input2: in std_logic;

	8
		input3: in std_logic;

	9
		output: out std_logic

	10
	);

	11
	end comb_ckt;

	12
	
	13
	architecture struct of comb_ckt is

	14
	
	15
	    component AND_GATE is		

	16
	    port(   A:	in std_logic;

	17
	    	    B:	in std_logic;

	18
	            F1:	out std_logic

	19
	    );

	20
	    end component;

	21
	
	22
	    component OR_GATE is		

			Error
	
		Row 23, Column 18
	
		"no declaration for "sstd_logic""
	
			Error
	
		Row 23, Column 12
	
		"(type of signal interface "x" is an erroneous type)"
	
	23
	    port(   X:	in sstd_logic;

	24
	    	    Y:	in std_logic;

	25
	    	    F2: out std_logic

	26
	    );

	27
	    end component;

	28
	
	29
	    signal wire: std_logic;		

	30
	
	31
	begin

	32
	
			Error
	
		Row 33, Column 44
	
		"no declaration for "insput2""
	
	33
	    Gate1: AND_GATE port map (A=>input1, B=>insput2, F1=>wire);

			Error
	
		Row 34, Column 32
	
		"can't associate 'wire' with signal interface "x""
	
			Error
	
		Row 34, Column 32
	
		"(type of 'wire' is std_logic)"
	
	34
	    Gate2: OR_GATE port map (X=>wire, Y=>input3, F2=>output);

	35
	
	36
	end struct;

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