Code formatting

Thanks to the tools integrated in TerosHDL is possible to format HDL code. A different formater is used if the file is Verilog or VHDL.

The currently supported formaters are:

Verilog

VHDL

iStyle

Standalone

Check the formatter configuration options

Usage instructions

  1. Open an SV/Verilog/VHDL file.

  2. Ctrl+Shift+i or click on the buttom with the tick to format the file.

  3. Save the file with the new format.