State machine designer

TerosHDL has a built-in state machine designer. A state machine diagram can be designed in a graphical environment and then exported to Verilog or VHDL code.

Aditionally the designed graph can be saved and imported in a JSON format.

Usage instructions

  1. Open the command palette Ctrl+Shift+P and select State machine designer

../_images/state_machine_designer_select.png
  1. Follow the instructions of the designer.

../_images/state_machine_designer_machine.gif