Template generator

With the template generator function you can generate code snippets from a module or entity.

Supported templates

Verilog

VHDL

Testbench

Testbench

cocotb

cocotb

VUnit

VUnit

Signals

Signals

Component

Component

Instance

Instance

Verilator

Usage instructions

  1. Open a Verilog/VHDL file and push the template generation button.

../_images/sample_templates_select.png
  1. Select the desired template from the list.

../_images/sample_templates_type.png
  1. The template will be stored in the clipboard and ready to be pasted Ctrl+v anywhere.