Entity: soc_reset_tb
- File: soc_reset_tb.vhdl
Diagram
Signals
| Name | Type | Description |
|---|---|---|
| ext_clk | std_ulogic | |
| pll_clk | std_ulogic | |
| pll_locked_in | std_ulogic | |
| ext_rst_in | std_ulogic | |
| pll_rst_out | std_ulogic | |
| rst_out | std_ulogic |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| clk_period | time | 10 ns | |
| test_vectors | test_vector_array | ( -- PLL not locked, reset button not pressed ('0', '1', '1', '1'), ('0', '1', '1', '1'), ('0', '1', '1', '1'), ('0', '1', '1', '1'), ('0', '1', '1', '1'), ('0', '1', '1', '1'), -- Reset is removed from the PLL ('0', '1', '0', '1'), ('0', '1', '0', '1'), ('0', '1', '0', '1'), -- At some point PLL comes out of reset ('1', '1', '0', '1'), ('1', '1', '0', '1'), ('1', '1', '0', '1'), ('1', '1', '0', '1'), ('1', '1', '0', '1'), ('1', '1', '0', '1'), -- Finally SOC comes out of reset ('1', '1', '0', '0'), ('1', '1', '0', '0'), -- PLL locked, reset button pressed ('1', '0', '0', '0'), ('1', '0', '0', '0'), ('1', '0', '0', '0'), ('1', '0', '1', '1'), -- PLL locked, reset button released ('1', '1', '1', '1'), ('1', '1', '1', '1'), ('1', '1', '1', '1'), ('1', '1', '1', '1'), ('1', '1', '1', '1'), ('1', '1', '1', '1'), ('1', '1', '0', '1'), ('1', '1', '0', '1'), ('1', '1', '0', '1'), ('1', '1', '0', '1'), ('1', '1', '0', '1'), ('1', '1', '0', '1'), -- Finally SOC comes out of reset ('1', '1', '0', '0') ) |
Types
| Name | Type | Description |
|---|---|---|
| test_vector | ||
| test_vector_array | array (natural range <>) of test_vector |
Processes
- clock: ( )
- stim: ( )
Instantiations
- soc_reset_0: work.soc_reset