Entity: toplevel

Diagram

integer MEMORY_SIZE string RAM_INIT_FILE boolean RESET_LOW positive CLK_FREQUENCY boolean HAS_FPU boolean HAS_BTC boolean USE_LITEDRAM boolean NO_BRAM boolean DISABLE_FLATTEN_CORE integer SPI_FLASH_OFFSET natural SPI_FLASH_DEF_CKDV boolean SPI_FLASH_DEF_QUAD natural LOG_LENGTH boolean UART_IS_16550 boolean USE_LITEETH boolean USE_LITESDCARD std_ulogic ext_clk std_ulogic ext_rst_n std_ulogic uart_main_rx std_ulogic eth_clocks_rx std_ulogic eth_int_n std_ulogic eth_rx_ctl std_ulogic_vector(3 downto 0) eth_rx_data std_ulogic sdcard_cd std_ulogic uart_main_tx std_ulogic led0 std_ulogic led1 std_ulogic led2 std_ulogic led3 std_ulogic led4 std_ulogic led5 std_ulogic led6 std_ulogic led7 std_ulogic spi_flash_cs_n std_ulogic spi_flash_mosi std_ulogic spi_flash_miso std_ulogic spi_flash_wp_n std_ulogic spi_flash_hold_n std_ulogic eth_clocks_tx std_ulogic eth_rst_n std_ulogic eth_mdio std_ulogic eth_mdc std_ulogic eth_tx_ctl std_ulogic_vector(3 downto 0) eth_tx_data std_ulogic_vector(3 downto 0) sdcard_data std_ulogic sdcard_cmd std_ulogic sdcard_clk std_ulogic sdcard_reset std_logic_vector(14 downto 0) ddram_a std_logic_vector(2 downto 0) ddram_ba std_logic ddram_ras_n std_logic ddram_cas_n std_logic ddram_we_n std_logic_vector(1 downto 0) ddram_dm std_logic_vector(15 downto 0) ddram_dq std_logic_vector(1 downto 0) ddram_dqs_p std_logic_vector(1 downto 0) ddram_dqs_n std_logic ddram_clk_p std_logic ddram_clk_n std_logic ddram_cke std_logic ddram_odt std_logic ddram_reset_n

Generics

Generic name Type Value Description
MEMORY_SIZE integer 16384
RAM_INIT_FILE string "firmware.hex"
RESET_LOW boolean true
CLK_FREQUENCY positive 100000000
HAS_FPU boolean true
HAS_BTC boolean true
USE_LITEDRAM boolean false
NO_BRAM boolean false
DISABLE_FLATTEN_CORE boolean false
SPI_FLASH_OFFSET integer 10485760
SPI_FLASH_DEF_CKDV natural 1
SPI_FLASH_DEF_QUAD boolean true
LOG_LENGTH natural 2048
UART_IS_16550 boolean true
USE_LITEETH boolean false
USE_LITESDCARD boolean false

Ports

Port name Direction Type Description
ext_clk in std_ulogic
ext_rst_n in std_ulogic
uart_main_tx out std_ulogic UART0 signals:
uart_main_rx in std_ulogic
led0 out std_ulogic LEDs
led1 out std_ulogic
led2 out std_ulogic
led3 out std_ulogic
led4 out std_ulogic
led5 out std_ulogic
led6 out std_ulogic
led7 out std_ulogic
spi_flash_cs_n out std_ulogic SPI
spi_flash_mosi inout std_ulogic
spi_flash_miso inout std_ulogic
spi_flash_wp_n inout std_ulogic
spi_flash_hold_n inout std_ulogic
eth_clocks_tx out std_ulogic Ethernet
eth_clocks_rx in std_ulogic
eth_rst_n out std_ulogic
eth_int_n in std_ulogic
eth_mdio inout std_ulogic
eth_mdc out std_ulogic
eth_rx_ctl in std_ulogic
eth_rx_data in std_ulogic_vector(3 downto 0)
eth_tx_ctl out std_ulogic
eth_tx_data out std_ulogic_vector(3 downto 0)
sdcard_data inout std_ulogic_vector(3 downto 0) SD card
sdcard_cmd inout std_ulogic
sdcard_clk out std_ulogic
sdcard_cd in std_ulogic
sdcard_reset out std_ulogic
ddram_a out std_logic_vector(14 downto 0) DRAM wires
ddram_ba out std_logic_vector(2 downto 0)
ddram_ras_n out std_logic
ddram_cas_n out std_logic
ddram_we_n out std_logic
ddram_dm out std_logic_vector(1 downto 0)
ddram_dq inout std_logic_vector(15 downto 0)
ddram_dqs_p inout std_logic_vector(1 downto 0)
ddram_dqs_n inout std_logic_vector(1 downto 0)
ddram_clk_p out std_logic
ddram_clk_n out std_logic
ddram_cke out std_logic
ddram_odt out std_logic
ddram_reset_n out std_logic

Signals

Name Type Description
soc_rst std_ulogic
pll_rst std_ulogic
system_clk std_ulogic Internal clock signals:
system_clk_locked std_ulogic
wb_ext_io_in wb_io_master_out External IOs from the SoC
wb_ext_io_out wb_io_slave_out
wb_ext_is_dram_csr std_ulogic
wb_ext_is_dram_init std_ulogic
wb_ext_is_eth std_ulogic
wb_ext_is_sdcard std_ulogic
wb_dram_in wishbone_master_out DRAM main data wishbone connection
wb_dram_out wishbone_slave_out
wb_dram_ctrl_out wb_io_slave_out DRAM control wishbone connection
ext_irq_eth std_ulogic LiteEth connection
wb_eth_out wb_io_slave_out
ext_irq_sdcard std_ulogic LiteSDCard connection
wb_sdcard_out wb_io_slave_out
wb_sddma_out wb_io_master_out
wb_sddma_in wb_io_slave_out
wb_sddma_nr wb_io_master_out
wb_sddma_ir wb_io_slave_out
wb_sddma_stb_sent std_ulogic for conversion from non-pipelined wishbone to pipelined
core_alt_reset std_ulogic Control/status
spi_sck std_ulogic SPI flash
spi_cs_n std_ulogic
spi_sdat_o std_ulogic_vector(3 downto 0)
spi_sdat_oe std_ulogic_vector(3 downto 0)
spi_sdat_i std_ulogic_vector(3 downto 0)

Constants

Name Type Value Description
BRAM_SIZE natural get_bram_size
PAYLOAD_SIZE natural get_payload_size

Functions

Description
Fixup various memory sizes based on generics

Instantiations