Entity: neorv32_cpu_cp_fpu
- File: neorv32_cpu_cp_fpu.vhd
Diagram
Description
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<< NEORV32 - CPU Co-Processor: Single-Prec. Floating Point Unit (RISC-V "Zfinx" Extension) >>
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The Zfinx floating-point extension uses the integer register file (x) for all FP operations.
See the official RISC-V specs (https://github.com/riscv/riscv-zfinx) for more information.
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Design Notes:
* This FPU is based on a multi-cycle architecture and is NOT suited for pipelined operations.
* The hardware design goal was SIZE (performance comes second). All shift operations are done
using an iterative approach (one bit per clock cycle, no barrel shifters!).
* Multiplication (FMUL instruction) will infer DSP blocks (if available).
* Subnormal numbers are not supported yet - they are "flushed to zero" before entering the
actual FPU core.
* Division and sqare root operations (FDIV, FSQRT) and fused multiply-accumulate operations
(F[N]MADD) are not supported yet - they will raise an illegal instruction exception.
* Rounding mode <100> ("round to nearest, ties to max magnitude") is not supported yet.
* Signaling NaNs (sNaN) will not be generated by the hardware at all. However, if inserted by
the programmer they are handled correctly.
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BSD 3-Clause License
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Copyright (c) 2021, Stephan Nolting. All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are
permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this list of
conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice, this list of
conditions and the following disclaimer in the documentation and/or other materials
provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors may be used to
endorse or promote products derived from this software without specific prior written
permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
OF THE POSSIBILITY OF SUCH DAMAGE.
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The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting
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Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | std_ulogic | global clock, rising edge |
| rstn_i | in | std_ulogic | global reset, low-active, async |
| ctrl_i | in | std_ulogic_vector(ctrl_width_c-1 downto 0) | main control bus |
| start_i | in | std_ulogic | trigger operation |
| cmp_i | in | std_ulogic_vector(1 downto 0) | comparator status |
| rs1_i | in | std_ulogic_vector(data_width_c-1 downto 0) | rf source 1 |
| rs2_i | in | std_ulogic_vector(data_width_c-1 downto 0) | rf source 2 |
| res_o | out | std_ulogic_vector(data_width_c-1 downto 0) | operation result |
| fflags_o | out | std_ulogic_vector(4 downto 0) | exception flags |
| valid_o | out | std_ulogic | data output valid |
Signals
| Name | Type | Description |
|---|---|---|
| cmd | cmd_t | |
| funct_ff | std_ulogic_vector(2 downto 0) | |
| ctrl_engine | ctrl_engine_t | |
| op_data | op_data_t | |
| op_class | op_class_t | |
| fpu_operands | fpu_operands_t | |
| cmp_ff | std_ulogic_vector(01 downto 0) | floating-point comparator -- |
| comp_equal_ff | std_ulogic | |
| comp_less_ff | std_ulogic | |
| fu_classify | fu_interface_t | |
| fu_compare | fu_interface_t | |
| fu_sign_inject | fu_interface_t | |
| fu_min_max | fu_interface_t | |
| fu_conv_f2i | fu_interface_t | |
| fu_addsub | fu_interface_t | |
| fu_mul | fu_interface_t | |
| fu_core_done | std_ulogic | FU operation completed |
| fu_conv_i2f | fu_i2f_interface_t | float result |
| multiplier | multiplier_t | |
| addsub | addsub_t | |
| normalizer | normalizer_t |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| op_class_c | std_ulogic_vector(2 downto 0) | "000" | |
| op_comp_c | std_ulogic_vector(2 downto 0) | "001" | |
| op_i2f_c | std_ulogic_vector(2 downto 0) | "010" | |
| op_f2i_c | std_ulogic_vector(2 downto 0) | "011" | |
| op_sgnj_c | std_ulogic_vector(2 downto 0) | "100" | |
| op_minmax_c | std_ulogic_vector(2 downto 0) | "101" | |
| op_addsub_c | std_ulogic_vector(2 downto 0) | "110" | |
| op_mul_c | std_ulogic_vector(2 downto 0) | "111" |
Types
| Name | Type | Description |
|---|---|---|
| cmd_t | commands (one-hot) -- | |
| ctrl_state_t | (S_IDLE, S_BUSY) |
co-processor control engine -- |
| ctrl_engine_t | ||
| op_data_t | floating-point operands -- | |
| op_class_t | ||
| fpu_operands_t | ||
| fu_interface_t | functional units interface -- | |
| fu_i2f_interface_t | integer-to-float -- | |
| multiplier_t | multiplier unit -- | |
| addsub_t | adder/subtractor unit -- | |
| normalizer_t | normalizer interface (normalization & rounding and int-to-float) -- |
Processes
- number_classifier: ( op_data )
Description
flush mantissa to zero if subnormal Number Classifier ---------------------------------------------------------------------- -------------------------------------------------------------------------------------------
- control_engine_fsm: ( rstn_i, clk_i )
Description
Co-Processor Control Engine ------------------------------------------------------------ -------------------------------------------------------------------------------------------
- float_comparator: ( rstn_i, clk_i )
Description
Floating-Point Comparator -------------------------------------------------------------- -------------------------------------------------------------------------------------------
- float_comparison: ( fpu_operands, ctrl_i, comp_equal_ff, comp_less_ff )
Description
Comparison (FEQ/FLT/FLE) --------------------------------------------------------------- -------------------------------------------------------------------------------------------
- min_max_select: ( fpu_operands, comp_less_ff, fu_compare, ctrl_i )
Description
does not generate exceptions here, but normalizer can generate exceptions Min/Max Select (FMIN/FMAX) ------------------------------------------------------------- -------------------------------------------------------------------------------------------
- sign_injector: ( ctrl_i, fpu_operands )
Description
Sign-Injection (FSGNJ) ----------------------------------------------------------------- -------------------------------------------------------------------------------------------
- convert_i2f: ( rstn_i, clk_i )
Description
Convert: [unsigned] Integer to Float (FCVT.W.S) ---------------------------------------- -------------------------------------------------------------------------------------------
- multiplier_core: ( rstn_i, clk_i )
Description
Multiplier Core (FMUL) ----------------------------------------------------------------- -------------------------------------------------------------------------------------------
- multiplier_class_core: ( rstn_i, clk_i )
Description
inexcat: not possible here result class --
- adder_subtractor_core: ( rstn_i, clk_i )
Description
Adder/Subtractor Core (FADD, FSUB) ----------------------------------------------------- -------------------------------------------------------------------------------------------
- adder_subtractor_class_core: ( rstn_i, clk_i )
Description
result class --
- normalizer_input_select: ( funct_ff, addsub, multiplier, fu_conv_i2f )
Description
FPU Core - Normalize & Round Normalizer Input ----------------------------------------------------------------------- -------------------------------------------------------------------------------------------
- output_gate: ( rstn_i, clk_i )
Description
FPU Core - Result Result Output to CPU Pipeline ---------------------------------------------------------- -------------------------------------------------------------------------------------------
Instantiations
- neorv32_cpu_cp_fpu_f2i_inst: neorv32_cpu_cp_fpu_f2i
Description
does not generate exceptions here, but normalizer can generate exceptions
Convert: Float to [unsigned] Integer (FCVT.S.W) ----------------------------------------
- neorv32_cpu_cp_fpu_normalizer_inst: neorv32_cpu_cp_fpu_normalizer
Description
Normalizer & Rounding Unit -------------------------------------------------------------