Entity: neorv32_debug_dm
- File: neorv32_debug_dm.vhd
Diagram
Description
#################################################################################################
<< NEORV32 - RISC-V-Compatible Debug Module (DM) >>
*
Compatible to the "Minimal RISC-V External Debug Spec. Version 0.13.2"
-> "Execution-based" debugging scheme #
*
Key features:
* register access commands only
* auto-execution commands
* for a single hart only
* 2 general purpose program buffer entries
* 1 general purpose data buffer entry
#
CPU access:
* ROM for "park loop" code
* program buffer
* data buffer
* control and status register
*
BSD 3-Clause License
#
Copyright (c) 2021, Stephan Nolting. All rights reserved.
#
Redistribution and use in source and binary forms, with or without modification, are
permitted provided that the following conditions are met:
#
1. Redistributions of source code must retain the above copyright notice, this list of
conditions and the following disclaimer.
#
2. Redistributions in binary form must reproduce the above copyright notice, this list of
conditions and the following disclaimer in the documentation and/or other materials
provided with the distribution.
#
3. Neither the name of the copyright holder nor the names of its contributors may be used to
endorse or promote products derived from this software without specific prior written
permission.
#
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
OF THE POSSIBILITY OF SUCH DAMAGE.
*
The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting
#################################################################################################
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | std_ulogic | global clock line |
| rstn_i | in | std_ulogic | global reset line, low-active |
| dmi_rstn_i | in | std_ulogic | debug module interface (DMI) -- |
| dmi_req_valid_i | in | std_ulogic | |
| dmi_req_ready_o | out | std_ulogic | DMI is allowed to make new requests when set |
| dmi_req_addr_i | in | std_ulogic_vector(06 downto 0) | |
| dmi_req_op_i | in | std_ulogic | 0=read, 1=write |
| dmi_req_data_i | in | std_ulogic_vector(31 downto 0) | |
| dmi_resp_valid_o | out | std_ulogic | response valid when set |
| dmi_resp_ready_i | in | std_ulogic | ready to receive respond |
| dmi_resp_data_o | out | std_ulogic_vector(31 downto 0) | |
| dmi_resp_err_o | out | std_ulogic | 0=ok, 1=error |
| cpu_addr_i | in | std_ulogic_vector(31 downto 0) | address |
| cpu_rden_i | in | std_ulogic | read enable |
| cpu_wren_i | in | std_ulogic | write enable |
| cpu_data_i | in | std_ulogic_vector(31 downto 0) | data in |
| cpu_data_o | out | std_ulogic_vector(31 downto 0) | data out |
| cpu_ack_o | out | std_ulogic | transfer acknowledge |
| cpu_ndmrstn_o | out | std_ulogic | soc reset |
| cpu_halt_req_o | out | std_ulogic | request hart to halt (enter debug mode) |
Signals
| Name | Type | Description |
|---|---|---|
| dm_ctrl | dm_ctrl_t | |
| dm_reg | dm_reg_t | |
| cpu_progbuf | cpu_progbuf_t | |
| dci | dci_t | |
| acc_en | std_ulogic | global access control -- |
| rden | std_ulogic | |
| wren | std_ulogic | |
| maddr | std_ulogic_vector(01 downto 0) | |
| data_buf | std_ulogic_vector(31 downto 0) | data buffer -- |
| prog_buf | prog_buf_t |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| nscratch_c | std_ulogic_vector(03 downto 0) | "0001" | number of dscratch* registers in CPU = 1 |
| dataaccess_c | std_ulogic | '1' | 1: abstract data is memory-mapped, 0: abstract data is CSR-mapped |
| datasize_c | std_ulogic_vector(03 downto 0) | "0001" | number of data registers in memory/CSR space = 1 |
| dataaddr_c | std_ulogic_vector(11 downto 0) | dm_data_base_c(11 downto 0) | signed base address of data registers in memory/CSR space |
| addr_data0_c | std_ulogic_vector(6 downto 0) | "000" & x"4" | available DMI registers -- |
| addr_dmcontrol_c | std_ulogic_vector(6 downto 0) | "001" & x"0" | |
| addr_dmstatus_c | std_ulogic_vector(6 downto 0) | "001" & x"1" | |
| addr_hartinfo_c | std_ulogic_vector(6 downto 0) | "001" & x"2" | |
| addr_abstractcs_c | std_ulogic_vector(6 downto 0) | "001" & x"6" | |
| addr_command_c | std_ulogic_vector(6 downto 0) | "001" & x"7" | |
| addr_abstractauto_c | std_ulogic_vector(6 downto 0) | "001" & x"8" | |
| addr_nextdm_c | std_ulogic_vector(6 downto 0) | "001" & x"d" | |
| addr_progbuf0_c | std_ulogic_vector(6 downto 0) | "010" & x"0" | |
| addr_progbuf1_c | std_ulogic_vector(6 downto 0) | "010" & x"1" | |
| addr_sbcs_c | std_ulogic_vector(6 downto 0) | "011" & x"8" | |
| addr_haltsum0_c | std_ulogic_vector(6 downto 0) | "100" & x"0" | |
| instr_nop_c | std_ulogic_vector(31 downto 0) | x"00000013" | nop |
| instr_lw_c | std_ulogic_vector(31 downto 0) | x"00002003" | lw zero, 0(zero) |
| instr_sw_c | std_ulogic_vector(31 downto 0) | x"00002023" | sw zero, 0(zero) |
| instr_ebreak_c | std_ulogic_vector(31 downto 0) | x"00100073" | ebreak |
| hi_abb_c | natural | 31 | high address boundary bit |
| lo_abb_c | natural | index_size_f(dm_size_c) | low address boundary bit |
| sreg_halt_ack_c | natural | 0 | -/w: CPU is halted in debug mode and waits in park loop |
| sreg_resume_req_c | natural | 1 | r/-: DM requests CPU to resume |
| sreg_resume_ack_c | natural | 2 | -/w: CPU starts resuming |
| sreg_execute_req_c | natural | 3 | r/-: DM requests to execute program buffer |
| sreg_execute_ack_c | natural | 4 | -/w: CPU starts to execute program buffer |
| sreg_exception_ack_c | natural | 5 | -/w: CPU has detected an exception |
| code_rom_file | code_rom_file_t | ( 00000000 => x"0180006f", 00000001 => x"7b241073", 00000002 => x"02000413", 00000003 => x"98802023", 00000004 => x"7b202473", 00000005 => x"00100073", 00000006 => x"7b241073", 00000007 => x"00100413", 00000008 => x"98802023", 00000009 => x"98002403", 00000010 => x"00847413", 00000011 => x"02041263", 00000012 => x"98002403", 00000013 => x"00247413", 00000014 => x"00041463", 00000015 => x"fe9ff06f", 00000016 => x"00400413", 00000017 => x"98802023", 00000018 => x"7b202473", 00000019 => x"7b200073", 00000020 => x"01000413", 00000021 => x"98802023", 00000022 => x"7b202473", 00000023 => x"0000100f", 00000024 => x"88000067", others => x"00100073" -- ebreak ) |
Types
| Name | Type | Description |
|---|---|---|
| dm_ctrl_state_t | (CMD_IDLE, CMD_EXE_CHECK, CMD_EXE_PREPARE, CMD_EXE_TRIGGER, CMD_EXE_BUSY, CMD_EXE_ERROR) |
debug module controller -- |
| dm_ctrl_t | ||
| progbuf_t | debug module DMI registers / access -- | |
| dm_reg_t | ||
| cpu_progbuf_t | cpu program buffer -- | |
| dci_t | ** CPU Bus Interface ** Debug Core Interface | |
| code_rom_file_t | code ROM containing "park loop" -- | |
| prog_buf_t | program buffer access -- |
Processes
- dm_controller: ( clk_i )
- dmi_write_access: ( rstn_i, clk_i )
Description
Debug Module Interface - Write Access -------------------------------------------------- -------------------------------------------------------------------------------------------
- dmi_read_access: ( clk_i )
Description
always ready for new read/write accesses Debug Module Interface - Read Access --------------------------------------------------- -------------------------------------------------------------------------------------------
- write_access: ( clk_i )
Description
Write Access --------------------------------------------------------------------------- -------------------------------------------------------------------------------------------
- read_access: ( clk_i )
Description
Read Access ---------------------------------------------------------------------------- -------------------------------------------------------------------------------------------