Entity: neorv32_dmem
- File: neorv32_dmem.vhd
Diagram
Description
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<< NEORV32 - Processor-internal data memory (DMEM) >>
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BSD 3-Clause License
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Copyright (c) 2021, Stephan Nolting. All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are
permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this list of
conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice, this list of
conditions and the following disclaimer in the documentation and/or other materials
provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors may be used to
endorse or promote products derived from this software without specific prior written
permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS
OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting
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Generics
| Generic name | Type | Value | Description |
|---|---|---|---|
| DMEM_BASE | std_ulogic_vector(31 downto 0) | memory base address | |
| DMEM_SIZE | natural | processor-internal instruction memory size in bytes |
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| clk_i | in | std_ulogic | global clock line |
| rden_i | in | std_ulogic | read enable |
| wren_i | in | std_ulogic | write enable |
| ben_i | in | std_ulogic_vector(03 downto 0) | byte write enable |
| addr_i | in | std_ulogic_vector(31 downto 0) | address |
| data_i | in | std_ulogic_vector(31 downto 0) | data in |
| data_o | out | std_ulogic_vector(31 downto 0) | data out |
| ack_o | out | std_ulogic | transfer acknowledge |
Signals
| Name | Type | Description |
|---|---|---|
| acc_en | std_ulogic | local signals -- |
| rdata | std_ulogic_vector(31 downto 0) | |
| rden | std_ulogic | |
| addr | std_ulogic_vector(index_size_f(DMEM_SIZE/4)-1 downto 0) | |
| mem_ram_b0 | mem8_t(0 to DMEM_SIZE/4-1) | -------------------------------------------------------------------------------------------------------------- -- The memory (RAM) is built from 4 individual byte-wide memories b0..b3, since some synthesis tools have -- problems with 32-bit memories that provide dedicated byte-enable signals AND/OR with multi-dimensional arrays. -- -------------------------------------------------------------------------------------------------------------- -- RAM - not initialized at all -- |
| mem_ram_b1 | mem8_t(0 to DMEM_SIZE/4-1) | |
| mem_ram_b2 | mem8_t(0 to DMEM_SIZE/4-1) | |
| mem_ram_b3 | mem8_t(0 to DMEM_SIZE/4-1) | |
| mem_ram_b0_rd | std_ulogic_vector(7 downto 0) | read data -- |
| mem_ram_b1_rd | std_ulogic_vector(7 downto 0) | read data -- |
| mem_ram_b2_rd | std_ulogic_vector(7 downto 0) | read data -- |
| mem_ram_b3_rd | std_ulogic_vector(7 downto 0) | read data -- |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| hi_abb_c | natural | 31 | high address boundary bit |
| lo_abb_c | natural | index_size_f(DMEM_SIZE) | low address boundary bit |
Processes
- mem_access: ( clk_i )
Description
word aligned Memory Access -------------------------------------------------------------------------- -------------------------------------------------------------------------------------------
- bus_feedback: ( clk_i )
Description
Bus Feedback --------------------------------------------------------------------------- -------------------------------------------------------------------------------------------