Entity: neorv32_fifo

Diagram

natural FIFO_DEPTH natural FIFO_WIDTH boolean FIFO_RSYNC boolean FIFO_SAFE std_ulogic clk_i std_ulogic rstn_i std_ulogic clear_i std_ulogic_vector(FIFO_WIDTH-1 downto 0) wdata_i std_ulogic we_i std_ulogic re_i std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0) level_o std_ulogic free_o std_ulogic_vector(FIFO_WIDTH-1 downto 0) rdata_o std_ulogic avail_o

Description

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<< NEORV32 - General Purpose FIFO Component >>

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BSD 3-Clause License

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Copyright (c) 2021, Stephan Nolting. All rights reserved.

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Redistribution and use in source and binary forms, with or without modification, are

permitted provided that the following conditions are met:

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1. Redistributions of source code must retain the above copyright notice, this list of

conditions and the following disclaimer.

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2. Redistributions in binary form must reproduce the above copyright notice, this list of

conditions and the following disclaimer in the documentation and/or other materials

provided with the distribution.

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3. Neither the name of the copyright holder nor the names of its contributors may be used to

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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS

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AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING

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OF THE POSSIBILITY OF SUCH DAMAGE.

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The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting

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Generics

Generic name Type Value Description
FIFO_DEPTH natural number of fifo entries; has to be a power of two; min 1
FIFO_WIDTH natural size of data elements in fifo
FIFO_RSYNC boolean false = async read; true = sync read
FIFO_SAFE boolean true = allow read/write only if entry available

Ports

Port name Direction Type Description
clk_i in std_ulogic clock, rising edge
rstn_i in std_ulogic async reset, low-active
clear_i in std_ulogic sync reset, high-active
level_o out std_ulogic_vector(index_size_f(FIFO_DEPTH) downto 0) fill level
wdata_i in std_ulogic_vector(FIFO_WIDTH-1 downto 0) write data
we_i in std_ulogic write enable
free_o out std_ulogic at least one entry is free when set
re_i in std_ulogic read enable
rdata_o out std_ulogic_vector(FIFO_WIDTH-1 downto 0) read data
avail_o out std_ulogic data available when set

Signals

Name Type Description
fifo fifo_t

Types

Name Type Description
fifo_data_t
fifo_t

Processes

Description
FIFO Control --------------------------------------------------------------------------- -------------------------------------------------------------------------------------------

Description
FIFO Memory ---------------------------------------------------------------------------- -------------------------------------------------------------------------------------------