Entity: neorv32_wishbone

Diagram

boolean MEM_INT_IMEM_EN natural MEM_INT_IMEM_SIZE boolean MEM_INT_DMEM_EN natural MEM_INT_DMEM_SIZE natural BUS_TIMEOUT boolean PIPE_MODE boolean BIG_ENDIAN boolean ASYNC_RX std_ulogic clk_i std_ulogic rstn_i std_ulogic src_i std_ulogic_vector(31 downto 0) addr_i std_ulogic rden_i std_ulogic wren_i std_ulogic_vector(03 downto 0) ben_i std_ulogic_vector(31 downto 0) data_i std_ulogic lock_i std_ulogic_vector(01 downto 0) priv_i std_ulogic_vector(31 downto 0) wb_dat_i std_ulogic wb_ack_i std_ulogic wb_err_i std_ulogic_vector(31 downto 0) data_o std_ulogic ack_o std_ulogic err_o std_ulogic_vector(02 downto 0) wb_tag_o std_ulogic_vector(31 downto 0) wb_adr_o std_ulogic_vector(31 downto 0) wb_dat_o std_ulogic wb_we_o std_ulogic_vector(03 downto 0) wb_sel_o std_ulogic wb_stb_o std_ulogic wb_cyc_o std_ulogic wb_lock_o

Description

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<< NEORV32 - External Bus Interface (WISHBONE) >>

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All bus accesses from the CPU, which do not target the internal IO region / the internal

bootloader / the internal instruction or data memories (if implemented), are delegated via

this Wishbone gateway to the external bus interface. Accessed peripherals can have a response

latency of up to BUS_TIMEOUT - 1 cycles.

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Even when all processor-internal memories and IO devices are disabled, the EXTERNAL address

space ENDS at address 0xffff0000 (begin of internal BOOTROM address space).

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BSD 3-Clause License

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Copyright (c) 2021, Stephan Nolting. All rights reserved.

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Redistribution and use in source and binary forms, with or without modification, are

permitted provided that the following conditions are met:

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1. Redistributions of source code must retain the above copyright notice, this list of

conditions and the following disclaimer.

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2. Redistributions in binary form must reproduce the above copyright notice, this list of

conditions and the following disclaimer in the documentation and/or other materials

provided with the distribution.

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3. Neither the name of the copyright holder nor the names of its contributors may be used to

endorse or promote products derived from this software without specific prior written

permission.

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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS

OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF

MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE

COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,

EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE

GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED

AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING

NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED

OF THE POSSIBILITY OF SUCH DAMAGE.

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The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting

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Generics

Generic name Type Value Description
MEM_INT_IMEM_EN boolean implement processor-internal instruction memory
MEM_INT_IMEM_SIZE natural size of processor-internal instruction memory in bytes
MEM_INT_DMEM_EN boolean implement processor-internal data memory
MEM_INT_DMEM_SIZE natural size of processor-internal data memory in bytes
BUS_TIMEOUT natural cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
PIPE_MODE boolean protocol: false=classic/standard wishbone mode, true=pipelined wishbone mode
BIG_ENDIAN boolean byte order: true=big-endian, false=little-endian
ASYNC_RX boolean use register buffer for RX data when false

Ports

Port name Direction Type Description
clk_i in std_ulogic global clock line
rstn_i in std_ulogic global reset line, low-active
src_i in std_ulogic access type (0: data, 1:instruction)
addr_i in std_ulogic_vector(31 downto 0) address
rden_i in std_ulogic read enable
wren_i in std_ulogic write enable
ben_i in std_ulogic_vector(03 downto 0) byte write enable
data_i in std_ulogic_vector(31 downto 0) data in
data_o out std_ulogic_vector(31 downto 0) data out
lock_i in std_ulogic exclusive access request
ack_o out std_ulogic transfer acknowledge
err_o out std_ulogic transfer error
priv_i in std_ulogic_vector(01 downto 0) current CPU privilege level
wb_tag_o out std_ulogic_vector(02 downto 0) request tag
wb_adr_o out std_ulogic_vector(31 downto 0) address
wb_dat_i in std_ulogic_vector(31 downto 0) read data
wb_dat_o out std_ulogic_vector(31 downto 0) write data
wb_we_o out std_ulogic read/write
wb_sel_o out std_ulogic_vector(03 downto 0) byte enable
wb_stb_o out std_ulogic strobe
wb_cyc_o out std_ulogic valid cycle
wb_lock_o out std_ulogic exclusive access request
wb_ack_i in std_ulogic transfer acknowledge
wb_err_i in std_ulogic transfer error

Signals

Name Type Description
int_imem_acc std_ulogic access control --
int_dmem_acc std_ulogic
int_boot_acc std_ulogic
xbus_access std_ulogic
ctrl ctrl_t
stb_int std_ulogic
cyc_int std_ulogic
rdata std_ulogic_vector(31 downto 0)
ack_gated std_ulogic async RX mode --
rdata_gated std_ulogic_vector(31 downto 0)

Constants

Name Type Value Description
timeout_en_c boolean boolean(BUS_TIMEOUT /= 0) timeout enabled if BUS_TIMEOUT > 0

Types

Name Type Description
ctrl_state_t (IDLE,
BUSY)		 bus arbiter
ctrl_t

Processes

Description
Bus Arbiter ----------------------------------------------------------------------------- -------------------------------------------------------------------------------------------