Entity: AlertLog_Demo_Hierarchy
- File: AlertLog_Demo_Hierarchy.vhd
Diagram
Description
File Name: AlertLog_Demo_Hierarchy.vhd Design Unit Name: AlertLog_Demo_Hierarchy Revision: STANDARD VERSION, 2015.01
Copyright (c) 2015 by SynthWorks Design Inc. All rights reserved.
Maintainer: Jim Lewis email: jim@synthworks.com Contributor(s): Jim Lewis email: jim@synthworks.com
Description: Demo showing use of hierarchy in AlertLogPkg Both TB and CPU use sublevels of hierarchy UART does not use sublevels of hierarchy Usage of block statements emulates a separate entity/architecture
Developed for: SynthWorks Design Inc. Training Courses 11898 SW 128th Ave. Tigard, Or 97223 http://www.SynthWorks.com
Revision History: Date Version Description 01/2015 2015.01 Refining tests 01/2020 2020.01 Updated Licenses to Apache
This file is part of OSVVM.
Copyright (c) 2015 - 2020 by SynthWorks Design Inc.
Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at
https://www.apache.org/licenses/LICENSE-2.0Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
Signals
| Name | Type | Description |
|---|---|---|
| Clk | std_logic |