Entity: cw_exp

Diagram

wire clk wire rstn wire tx_try_complete wire [31:0] cw_combined wire start_retrans wire [1:0] tx_queue_idx [3:0] cw_exp

Description

`define DEBUG_PREFIX (mark_debug="true",DONT_TOUCH="TRUE")

Ports

Port name Direction Type Description
clk input wire
rstn input wire
tx_try_complete input wire
cw_combined input wire [31:0]
start_retrans input wire
tx_queue_idx input wire [1:0]
cw_exp input [3:0]

Signals

Name Type Description
cw_min reg [3:0]
cw_max reg [3:0]
tx_queue_idx_reg reg [1:0]
cw_update reg

Processes

Type: always

Type: always

Type: always