Entity: openofdm_tx

Diagram

integer C_S00_AXI_DATA_WIDTH integer C_S00_AXI_ADDR_WIDTH wire clk wire phy_tx_arestn wire phy_tx_start wire [63:0] bram_din wire result_iq_hold wire s00_axi_aclk wire s00_axi_aresetn wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr wire [2 : 0] s00_axi_awprot wire s00_axi_awvalid wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb wire s00_axi_wvalid wire s00_axi_bready wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr wire [2 : 0] s00_axi_arprot wire s00_axi_arvalid wire s00_axi_rready wire phy_tx_done wire phy_tx_started wire [9:0] bram_addr wire result_iq_valid wire [15:0] result_i wire [15:0] result_q wire s00_axi_awready wire s00_axi_wready wire [1 : 0] s00_axi_bresp wire s00_axi_bvalid wire s00_axi_arready wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata wire [1 : 0] s00_axi_rresp wire s00_axi_rvalid

Description

Generics

Generic name Type Value Description
C_S00_AXI_DATA_WIDTH integer 32
C_S00_AXI_ADDR_WIDTH integer 7

Ports

Port name Direction Type Description
clk input wire
phy_tx_arestn input wire
phy_tx_start input wire
phy_tx_done output wire
phy_tx_started output wire
bram_din input wire [63:0]
bram_addr output wire [9:0]
result_iq_hold input wire
result_iq_valid output wire
result_i output wire [15:0]
result_q output wire [15:0]
s00_axi_aclk input wire
s00_axi_aresetn input wire
s00_axi_awaddr input wire [C_S00_AXI_ADDR_WIDTH-1 : 0]
s00_axi_awprot input wire [2 : 0]
s00_axi_awvalid input wire
s00_axi_awready output wire
s00_axi_wdata input wire [C_S00_AXI_DATA_WIDTH-1 : 0]
s00_axi_wstrb input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0]
s00_axi_wvalid input wire
s00_axi_wready output wire
s00_axi_bresp output wire [1 : 0]
s00_axi_bvalid output wire
s00_axi_bready input wire
s00_axi_araddr input wire [C_S00_AXI_ADDR_WIDTH-1 : 0]
s00_axi_arprot input wire [2 : 0]
s00_axi_arvalid input wire
s00_axi_arready output wire
s00_axi_rdata output wire [C_S00_AXI_DATA_WIDTH-1 : 0]
s00_axi_rresp output wire [1 : 0]
s00_axi_rvalid output wire
s00_axi_rready input wire

Signals

Name Type Description
slv_reg0 wire [(C_S00_AXI_DATA_WIDTH-1):0] reg0~19 for config write; from reg20 for reading status
slv_reg1 wire [(C_S00_AXI_DATA_WIDTH-1):0]
slv_reg2 wire [(C_S00_AXI_DATA_WIDTH-1):0]
slv_reg20 wire [(C_S00_AXI_DATA_WIDTH-1):0] read openofdm rx core internal state

Instantiations

Description

wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg21;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg22;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg23;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg24;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg25;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg26;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg27;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg28;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg29;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg30;
wire [(C_S00_AXI_DATA_WIDTH-1):0] slv_reg31;
*/

Description
assign bram_wen = 0;