Entity: side_ch_control

Diagram

integer TSF_TIMER_WIDTH integer GPIO_STATUS_WIDTH integer RSSI_HALF_DB_WIDTH integer C_S_AXI_DATA_WIDTH integer IQ_DATA_WIDTH integer C_S_AXIS_TDATA_WIDTH integer MAX_NUM_DMA_SYMBOL integer MAX_BIT_NUM_DMA_SYMBOL wire clk wire rstn wire [(GPIO_STATUS_WIDTH-1):0] gpio_status wire signed [(RSSI_HALF_DB_WIDTH-1):0] rssi_half_db wire [(TSF_TIMER_WIDTH-1):0] tsf_runtime_val wire [(2*IQ_DATA_WIDTH-1):0] openofdm_tx_iq0 wire [(2*IQ_DATA_WIDTH-1):0] openofdm_tx_iq1 wire openofdm_tx_iq_valid wire [(2*IQ_DATA_WIDTH-1):0] tx_intf_iq0 wire [(2*IQ_DATA_WIDTH-1):0] tx_intf_iq1 wire tx_intf_iq_valid wire [(2*IQ_DATA_WIDTH-1):0] iq0 wire [(2*IQ_DATA_WIDTH-1):0] iq1 wire iq_strobe wire demod_is_ongoing wire ofdm_symbol_eq_out_pulse wire long_preamble_detected wire short_preamble_detected wire ht_unsupport wire [7:0] pkt_rate wire [15:0] pkt_len wire [(2*IQ_DATA_WIDTH-1):0] csi wire csi_valid wire signed [31:0] phase_offset_taken wire [(2*IQ_DATA_WIDTH-1):0] equalizer wire equalizer_valid wire pkt_header_valid wire pkt_header_valid_strobe wire [31:0] FC_DI wire FC_DI_valid wire [47:0] addr1 wire addr1_valid wire [47:0] addr2 wire addr2_valid wire [47:0] addr3 wire addr3_valid wire fcs_in_strobe wire fcs_ok wire block_rx_dma_to_ps wire block_rx_dma_to_ps_valid wire phy_tx_start wire tx_pkt_need_ack wire phy_tx_started wire phy_tx_done wire tx_bb_is_ongoing wire tx_rf_is_ongoing wire slv_reg_wren_signal wire [4:0] axi_awaddr_core wire iq_capture wire [1:0] iq_capture_cfg wire [4:0] iq_trigger_select wire iq_trigger_free_run_flag wire [1:0] iq_source_select wire [(IQ_DATA_WIDTH-1):0] rssi_or_iq_th wire [(GPIO_STATUS_WIDTH-2):0] gain_th wire [MAX_BIT_NUM_DMA_SYMBOL-1 : 0] pre_trigger_len wire [MAX_BIT_NUM_DMA_SYMBOL-1 : 0] iq_len_target wire [15 : 0] FC_target wire [C_S_AXI_DATA_WIDTH-1 : 0] addr1_target wire [C_S_AXI_DATA_WIDTH-1 : 0] addr2_target wire [3:0] match_cfg wire [3:0] num_eq wire [1:0] m_axis_start_mode wire m_axis_start_ext_trigger wire [C_S_AXIS_TDATA_WIDTH-1 : 0] data_to_pl wire [MAX_BIT_NUM_DMA_SYMBOL-1 : 0] s_axis_data_count wire emptyn_to_pl wire S_AXIS_TVALID wire S_AXIS_TLAST wire M_AXIS_TVALID wire M_AXIS_TLAST wire pl_ask_data wire m_axis_start_1trans wire [C_S_AXIS_TDATA_WIDTH-1 : 0] data_to_ps wire data_to_ps_valid wire [MAX_BIT_NUM_DMA_SYMBOL-1 : 0] m_axis_data_count wire fulln_to_pl wire [31:0] MAX_NUM_DMA_SYMBOL_UDP_debug wire [31:0] MAX_NUM_DMA_SYMBOL_debug

Description

Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; `define DEBUG_PREFIX (mark_debug="true",DONT_TOUCH="TRUE")

Generics

Generic name Type Value Description
TSF_TIMER_WIDTH integer 64 according to 802.11 standard
GPIO_STATUS_WIDTH integer 8
RSSI_HALF_DB_WIDTH integer 11
C_S_AXI_DATA_WIDTH integer 32
IQ_DATA_WIDTH integer 16
C_S_AXIS_TDATA_WIDTH integer 64
MAX_NUM_DMA_SYMBOL integer 8192
MAX_BIT_NUM_DMA_SYMBOL integer 14

Ports

Port name Direction Type Description
clk input wire
rstn input wire
gpio_status input wire [(GPIO_STATUS_WIDTH-1):0] from pl
rssi_half_db input wire signed [(RSSI_HALF_DB_WIDTH-1):0]
tsf_runtime_val input wire [(TSF_TIMER_WIDTH-1):0]
openofdm_tx_iq0 input wire [(2*IQ_DATA_WIDTH-1):0]
openofdm_tx_iq1 input wire [(2*IQ_DATA_WIDTH-1):0]
openofdm_tx_iq_valid input wire
tx_intf_iq0 input wire [(2*IQ_DATA_WIDTH-1):0]
tx_intf_iq1 input wire [(2*IQ_DATA_WIDTH-1):0]
tx_intf_iq_valid input wire
iq0 input wire [(2*IQ_DATA_WIDTH-1):0]
iq1 input wire [(2*IQ_DATA_WIDTH-1):0]
iq_strobe input wire
demod_is_ongoing input wire
ofdm_symbol_eq_out_pulse input wire
long_preamble_detected input wire
short_preamble_detected input wire
ht_unsupport input wire
pkt_rate input wire [7:0]
pkt_len input wire [15:0]
csi input wire [(2*IQ_DATA_WIDTH-1):0]
csi_valid input wire
phase_offset_taken input wire signed [31:0]
equalizer input wire [(2*IQ_DATA_WIDTH-1):0]
equalizer_valid input wire
pkt_header_valid input wire
pkt_header_valid_strobe input wire
FC_DI input wire [31:0]
FC_DI_valid input wire
addr1 input wire [47:0]
addr1_valid input wire
addr2 input wire [47:0]
addr2_valid input wire
addr3 input wire [47:0]
addr3_valid input wire
fcs_in_strobe input wire
fcs_ok input wire
block_rx_dma_to_ps input wire
block_rx_dma_to_ps_valid input wire
phy_tx_start input wire from tx
tx_pkt_need_ack input wire
phy_tx_started input wire
phy_tx_done input wire
tx_bb_is_ongoing input wire
tx_rf_is_ongoing input wire
slv_reg_wren_signal input wire to capture m axis num dma symbol write, so that auto trigger start
axi_awaddr_core input wire [4:0]
iq_capture input wire
iq_capture_cfg input wire [1:0]
iq_trigger_select input wire [4:0]
iq_trigger_free_run_flag input wire
iq_source_select input wire [1:0]
rssi_or_iq_th input wire [(IQ_DATA_WIDTH-1):0]
gain_th input wire [(GPIO_STATUS_WIDTH-2):0]
pre_trigger_len input wire [MAX_BIT_NUM_DMA_SYMBOL-1 : 0]
iq_len_target input wire [MAX_BIT_NUM_DMA_SYMBOL-1 : 0]
FC_target input wire [15 : 0]
addr1_target input wire [C_S_AXI_DATA_WIDTH-1 : 0]
addr2_target input wire [C_S_AXI_DATA_WIDTH-1 : 0]
match_cfg input wire [3:0]
num_eq input wire [3:0]
m_axis_start_mode input wire [1:0]
m_axis_start_ext_trigger input wire
data_to_pl input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] s_axis
pl_ask_data output wire
s_axis_data_count input wire [MAX_BIT_NUM_DMA_SYMBOL-1 : 0]
emptyn_to_pl input wire
S_AXIS_TVALID input wire
S_AXIS_TLAST input wire
m_axis_start_1trans output wire m_axis
data_to_ps output wire [C_S_AXIS_TDATA_WIDTH-1 : 0]
data_to_ps_valid output wire
m_axis_data_count output wire [MAX_BIT_NUM_DMA_SYMBOL-1 : 0]
fulln_to_pl output wire
MAX_NUM_DMA_SYMBOL_UDP_debug output wire [31:0]
MAX_NUM_DMA_SYMBOL_debug output wire [31:0]
M_AXIS_TVALID input wire
M_AXIS_TLAST input wire

Signals

Name Type Description
ht_flag wire
ht_flag_capture reg
rate_mcs wire [3:0]
N_DBPS reg [8:0]
ht_rst reg
last_ofdm_symbol_flag reg
num_bit_decoded reg [19:0]
num_bit_target wire [19:0]
ofdm_rx_state reg [1:0]
csi_valid_reg reg
capture_src_flag reg
side_info_count reg [8:0]
num_eq_count reg [3:0]
side_ch_state reg [3:0]
side_ch_state_old reg [3:0]
num_dma_symbol_per_trans wire [MAX_BIT_NUM_DMA_SYMBOL-1 : 0]
num_dma_symbol_reg_wr_is_onging wire
num_dma_symbol_reg_wr_is_onging_reg reg
num_dma_symbol_reg_wr_is_onging_reg1 reg
m_axis_start_auto_trigger wire
tsf_val_lock_by_sig reg [(TSF_TIMER_WIDTH-1):0]
demod_is_ongoing_reg reg
FC_DI_valid_reg reg
addr1_valid_reg reg
addr2_valid_reg reg
m_axis_start_1trans_reg reg
pl_ask_data_reg reg
data_to_ps_reg reg [C_S_AXIS_TDATA_WIDTH-1 : 0]
data_to_ps_valid_reg reg
pkt_begin_rst wire
side_info_fifo_rst wire
side_info_fifo_dout wire [(2*IQ_DATA_WIDTH-1):0]
side_info_fifo_din wire [(2*IQ_DATA_WIDTH-1):0]
side_info_fifo_empty wire
side_info_fifo_full wire
side_info_fifo_rd_en reg
side_info_fifo_wr_en wire
side_info_fifo_rd_data_count wire [9:0]
side_info_fifo_wr_data_count wire [9:0]
side_info_csi reg [C_S_AXIS_TDATA_WIDTH-1 : 0]
side_info_csi_valid reg
side_info_iq_dpram_in wire [C_S_AXIS_TDATA_WIDTH-1 : 0]
side_info_iq_dpram wire [C_S_AXIS_TDATA_WIDTH-1 : 0]
side_info_iq reg [C_S_AXIS_TDATA_WIDTH-1 : 0]
side_info_iq_valid_tmp reg
side_info_iq_valid reg
side_info wire [C_S_AXIS_TDATA_WIDTH-1 : 0]
side_info_valid wire
iq0_inner wire [(2*IQ_DATA_WIDTH-1):0]
iq1_inner wire [(2*IQ_DATA_WIDTH-1):0]
iq_strobe_inner wire
iq_waddr reg [(bit_num-1):0]
iq_raddr reg [(bit_num-1):0]
iq1_i_abs wire [(IQ_DATA_WIDTH-1):0]
rssi_th wire [(RSSI_HALF_DB_WIDTH-1):0]
rssi_posedge reg
rssi_negedge reg
agc_lock_to_unlock reg
agc_unlock_to_lock reg
gain_posedge reg
gain_negedge reg
iq_trigger reg
tsf_val_lock_by_iq_trigger reg [(TSF_TIMER_WIDTH-1):0]
iq_count reg [(bit_num-1):0]
iq_state reg [1:0]
gpio_status_reg reg [(GPIO_STATUS_WIDTH-1):0]
rssi_half_db_reg reg signed [(RSSI_HALF_DB_WIDTH-1):0]
tx_bb_is_ongoing_reg reg
tx_rf_is_ongoing_reg reg
tx_bb_is_ongoing_posedge reg
tx_bb_is_ongoing_negedge reg
tx_rf_is_ongoing_posedge reg
tx_rf_is_ongoing_negedge reg
subcarrier_mask reg [63:0]
ALMOSTEMPTY wire fifo to capture side info (csi, equalizer, etc)
ALMOSTFULL wire
RDERR wire
WRERR wire
WRCOUNT wire [8:0]

Constants

Name Type Value Description
MAX_NUM_DMA_SYMBOL_UDP integer undefined Max UDP 65507 bytes; (65507/8) = 8188
bit_num integer clogb2(MAX_NUM_DMA_SYMBOL)-1
SUBCARRIER_MASK 64'b1111111111111111111111111100000000000111111111111111111111111110 mask[0] is DC, mask[1:26] -> 1,…, 26 mask[38:63] -> -26,…, -1
HT_SUBCARRIER_MASK 64'b1111111111111111111111111111000000011111111111111111111111111110
PILOT_MASK 64'b0000001000000000000010000000000000000000001000000000000010000000 -7, -21, 21, 7
DATA_SUBCARRIER_MASK SUBCARRIER_MASK ^ PILOT_MASK
HT_DATA_SUBCARRIER_MASK HT_SUBCARRIER_MASK ^ PILOT_MASK
CSI_LEN integer 56 length of single CSI
EQUALIZER_LEN integer (56-4) for non HT, four {32767,32767} will be padded to achieve 52 (non HT should have 48)
HEADER_LEN integer 2 timestamp and freq offset
OFDM_RX_INIT [1:0] 2'b00
OFDM_RX_COUNT [1:0] 2'b01
OFDM_RX_END [1:0] 2'b10
IQ_WAIT_FOR_CONDITION [1:0] 2'b00
IQ_PREPARE_TO_M_AXIS [1:0] 2'b01
IQ_HEADER_TO_M_AXIS [1:0] 2'b10
IQ_INFO_TO_M_AXIS [1:0] 2'b11
WAIT_FOR_CONDITION [3:0] 4'b0000
WAIT_FOR_CONDITION1 [3:0] 4'b0001
WAIT_FOR_CONDITION2 [3:0] 4'b0010
WAIT_FOR_CAPTURE_DONE [3:0] 4'b0011
PREPARE_TO_M_AXIS [3:0] 4'b0100
HEADER_TO_M_AXIS [3:0] 4'b0101
HEADER1_TO_M_AXIS [3:0] 4'b0110
CSI_INFO_TO_M_AXIS [3:0] 4'b0111
EQ_INFO_TO_M_AXIS [3:0] 4'b1000

Functions

Processes

Type: always

Type: always

Description
state machine tracking the rx procedure and give the last ofdm symbol indicator 1. decode end; 2 header invalid; 3 ht unsupport

Type: always

Description
generate multiplexing control signal to write csi/equalizer to fifo

Type: always

Description
sequencer and state machin to stream iq from dpram to m axis by generating iq_waddr, iq_raddr, side_info_iq and side_info_iq_valid

Type: always

Description
state machine to put captured side info to the fifo of m_axis

Type: always

Description
for m_axis_start_auto_trigger. used by both csi and iq

Type: always

Description
,data_transfer_control)

Instantiations

Description
dpram to buffer the iq, gpio_status, rssi_half_db before trigger

State machines

  • state machine tracking the rx procedure and give the last ofdm symbol indicator
  1. decode end; 2 header invalid; 3 ht unsupport
undefined
  • sequencer and state machin to stream iq from dpram to m axis by
    generating iq_waddr, iq_raddr, side_info_iq and side_info_iq_valid
undefined
  • state machine to put captured side info to the fifo of m_axis
undefined