Entity: tx_bit_intf

Diagram

integer C_S00_AXIS_TDATA_WIDTH integer WIFI_TX_BRAM_ADDR_WIDTH integer WIFI_TX_BRAM_DATA_WIDTH integer WIFI_TX_BRAM_WEN_WIDTH wire rstn wire clk wire [(C_S00_AXIS_TDATA_WIDTH-1):0] data_from_s_axis wire emptyn_from_s_axis wire auto_start_mode wire [9:0] num_dma_symbol_th wire [31:0] num_dma_symbol_total wire [1:0] tx_queue_idx_indication_from_ps wire s_axis_recv_data_from_high wire [31:0] cts_toself_config wire [13:0] send_cts_toself_wait_sifs_top wire [47:0] mac_addr wire tx_try_complete wire retrans_in_progress wire start_retrans wire start_tx_ack wire tx_control_state_idle wire high_tx_allowed0 wire high_tx_allowed1 wire high_tx_allowed2 wire high_tx_allowed3 wire tx_bb_is_ongoing wire ack_tx_flag wire wea_from_xpu wire [9:0] addra_from_xpu wire [(C_S00_AXIS_TDATA_WIDTH-1):0] dina_from_xpu wire tx_end_from_acc wire [(WIFI_TX_BRAM_ADDR_WIDTH-1):0] bram_addr wire tsf_pulse_1M wire ask_data_from_s_axis wire [1:0] tx_queue_idx [1:0] linux_prio wire start wire [6:0] num_dma_symbol_fifo_data_count0 wire [6:0] num_dma_symbol_fifo_data_count1 wire [6:0] num_dma_symbol_fifo_data_count2 wire [6:0] num_dma_symbol_fifo_data_count3 wire tx_iq_fifo_empty wire tx_pkt_need_ack quit_retrans high_trigger wire [3:0] tx_pkt_retrans_limit [9:0] tx_pkt_sn wire [(WIFI_TX_BRAM_DATA_WIDTH-1):0] douta cts_toself_bb_is_ongoing cts_toself_rf_is_ongoing wire [(WIFI_TX_BRAM_DATA_WIDTH-1):0] bram_data_to_acc

Description

Xianjun jiao. putaoshu@msn.com; xianjun.jiao@imec.be; `define DEBUG_PREFIX (mark_debug="true",DONT_TOUCH="TRUE")

Generics

Generic name Type Value Description
C_S00_AXIS_TDATA_WIDTH integer 64
WIFI_TX_BRAM_ADDR_WIDTH integer 10
WIFI_TX_BRAM_DATA_WIDTH integer 64
WIFI_TX_BRAM_WEN_WIDTH integer 8

Ports

Port name Direction Type Description
rstn input wire
clk input wire
data_from_s_axis input wire [(C_S00_AXIS_TDATA_WIDTH-1):0]
ask_data_from_s_axis output wire
emptyn_from_s_axis input wire
tx_queue_idx output wire [1:0]
linux_prio output [1:0]
auto_start_mode input wire input wire src_indication,//0-s_axis-->phy_tx-->iq-->duc; 1-s_axis-->iq-->duc
num_dma_symbol_th input wire [9:0]
num_dma_symbol_total input wire [31:0]
tx_queue_idx_indication_from_ps input wire [1:0]
s_axis_recv_data_from_high input wire
start output wire
num_dma_symbol_fifo_data_count0 output wire [6:0]
num_dma_symbol_fifo_data_count1 output wire [6:0]
num_dma_symbol_fifo_data_count2 output wire [6:0]
num_dma_symbol_fifo_data_count3 output wire [6:0]
tx_iq_fifo_empty output wire
cts_toself_config input wire [31:0]
send_cts_toself_wait_sifs_top input wire [13:0] between cts and following frame, there should be a sifs waiting period
mac_addr input wire [47:0]
tx_try_complete input wire
retrans_in_progress input wire
start_retrans input wire
start_tx_ack input wire
tx_control_state_idle input wire
high_tx_allowed0 input wire
high_tx_allowed1 input wire
high_tx_allowed2 input wire
high_tx_allowed3 input wire
tx_bb_is_ongoing input wire
ack_tx_flag input wire
wea_from_xpu input wire
addra_from_xpu input wire [9:0]
dina_from_xpu input wire [(C_S00_AXIS_TDATA_WIDTH-1):0]
tx_pkt_need_ack output wire
quit_retrans output
high_trigger output
tx_pkt_retrans_limit output wire [3:0]
tx_pkt_sn output [9:0]
douta output wire [(WIFI_TX_BRAM_DATA_WIDTH-1):0] output reg [15:0] tx_pkt_num_dma_byte,
cts_toself_bb_is_ongoing output
cts_toself_rf_is_ongoing output
tx_end_from_acc input wire port to phy_tx
bram_data_to_acc output wire [(WIFI_TX_BRAM_DATA_WIDTH-1):0]
bram_addr input wire [(WIFI_TX_BRAM_ADDR_WIDTH-1):0]
tsf_pulse_1M input wire

Signals

Name Type Description
high_tx_ctl_state reg [2:0]
high_tx_ctl_state_old reg [2:0]
send_cts_toself_wait_count reg [13:0]
wr_counter reg [12:0]
read_from_s_axis_en reg
wea_high wire
wea wire
addra wire [9:0]
dina wire [(C_S00_AXIS_TDATA_WIDTH-1):0]
bram_data_to_acc_int wire [(WIFI_TX_BRAM_DATA_WIDTH-1):0]
wea_internal reg
addra_internal reg [12:0]
dina_internal reg [(C_S00_AXIS_TDATA_WIDTH-1):0]
num_dma_symbol_fifo_rd_data0 wire [63:0]
num_dma_symbol_fifo_rd_data1 wire [63:0]
num_dma_symbol_fifo_rd_data2 wire [63:0]
num_dma_symbol_fifo_rd_data3 wire [63:0]
num_dma_symbol_total_current reg [63:0]
num_dma_symbol_total_rden0 reg
num_dma_symbol_total_rden1 reg
num_dma_symbol_total_rden2 reg
num_dma_symbol_total_rden3 reg
num_dma_symbol_total_wren0 reg
num_dma_symbol_total_wren1 reg
num_dma_symbol_total_wren2 reg
num_dma_symbol_total_wren3 reg
num_dma_symbol_fifo_empty0 wire
num_dma_symbol_fifo_empty1 wire
num_dma_symbol_fifo_empty2 wire
num_dma_symbol_fifo_empty3 wire
num_dma_symbol_fifo_full0 wire
num_dma_symbol_fifo_full1 wire
num_dma_symbol_fifo_full2 wire
num_dma_symbol_fifo_full3 wire
s_axis_recv_data_from_high_valid wire
tx_queue_idx_reg reg [1:0]
start_delay0 reg
start_delay1 reg
start_delay2 reg
start_delay3 reg
start_delay4 reg
start_delay5 reg
tx_try_complete_dl0 reg
tx_try_complete_dl1 reg
tx_try_complete_dl2 reg
tx_try_complete_dl_pulses wire
s_axis_recv_data_from_high_delay reg
cts_toself_rate reg [3:0]
cts_toself_signal_parity wire
cts_toself_signal_len wire [11:0]
mac_addr_reg reg [47:0]
send_cts_toself_wait_sifs_top_scale reg [13:0]

Constants

Name Type Value Description
WAIT_TO_TRIG [2:0] 3'b000
WAIT_CHANCE [2:0] 3'b001
PREPARE_TX_FETCH [2:0] 3'b010
PREPARE_TX_JUDGE [2:0] 3'b011
DO_CTS_TOSELF [2:0] 3'b100
WAIT_SIFS [2:0] 3'b101
DO_TX [2:0] 3'b110
WAIT_TX_COMP [2:0] 3'b111

Processes

Type: always

Description
state machine to do tx for high layer if high_tx_allowed

Type: always

Description
// watch dog for debug (* mark_debug = "true" ) reg [11:0] watch_dog_timer; always @(posedge clk) begin if ( rstn == 0 || (high_tx_ctl_state==DO_TX && high_tx_ctl_state_old!=DO_TX) ) begin watch_dog_timer <= 0; end else if ( high_tx_ctl_state==DO_TX ) begin watch_dog_timer<=(tsf_pulse_1M?(watch_dog_timer+1):watch_dog_timer); end end // watch dog for duplicated sn ( mark_debug = "true" ) reg [9:0] duplicated_sn; ( mark_debug = "true" *) reg duplicated_sn_catch; always @(posedge clk) begin if ( rstn == 0 ) begin duplicated_sn <= 10'd123; duplicated_sn_catch <= 0; end else if (tx_try_complete) begin duplicated_sn <= tx_pkt_sn; duplicated_sn_catch <= (duplicated_sn==tx_pkt_sn?1:0); end end store num_dma_symbol_total into fifo

Instantiations

Description
fifio to store num_dma_symbol_total each time s_axis_recv_data_from_high becomes high
fifo64_1clk_dep64 fifo64_1clk_dep64_i0 (// only store num_dma_symbol from high layer, not aware ack pkt
.CLK(clk),
.DATAO(num_dma_symbol_fifo_rd_data0),
.DI({cts_toself_config,num_dma_symbol_total}),
.EMPTY(num_dma_symbol_fifo_empty0),
.FULL(num_dma_symbol_fifo_full0),
.RDEN(num_dma_symbol_total_rden0),
.RST(!rstn),
.WREN(num_dma_symbol_total_wren0),
.data_count(num_dma_symbol_fifo_data_count0)
);

Description
fifio to store num_dma_symbol_total each time s_axis_recv_data_from_high becomes high
fifo64_1clk_dep64 fifo64_1clk_dep64_i1 (// only store num_dma_symbol from high layer, not aware ack pkt
.CLK(clk),
.DATAO(num_dma_symbol_fifo_rd_data1),
.DI({cts_toself_config,num_dma_symbol_total}),
.EMPTY(num_dma_symbol_fifo_empty1),
.FULL(num_dma_symbol_fifo_full1),
.RDEN(num_dma_symbol_total_rden1),
.RST(!rstn),
.WREN(num_dma_symbol_total_wren1),
.data_count(num_dma_symbol_fifo_data_count1)
);

Description
fifio to store num_dma_symbol_total each time s_axis_recv_data_from_high becomes high
fifo64_1clk_dep64 fifo64_1clk_dep64_i2 (// only store num_dma_symbol from high layer, not aware ack pkt
.CLK(clk),
.DATAO(num_dma_symbol_fifo_rd_data2),
.DI({cts_toself_config,num_dma_symbol_total}),
.EMPTY(num_dma_symbol_fifo_empty2),
.FULL(num_dma_symbol_fifo_full2),
.RDEN(num_dma_symbol_total_rden2),
.RST(!rstn),
.WREN(num_dma_symbol_total_wren2),
.data_count(num_dma_symbol_fifo_data_count2)
);

Description
fifio to store num_dma_symbol_total each time s_axis_recv_data_from_high becomes high
fifo64_1clk_dep64 fifo64_1clk_dep64_i3 (// only store num_dma_symbol from high layer, not aware ack pkt
.CLK(clk),
.DATAO(num_dma_symbol_fifo_rd_data3),
.DI({cts_toself_config,num_dma_symbol_total}),
.EMPTY(num_dma_symbol_fifo_empty3),
.FULL(num_dma_symbol_fifo_full3),
.RDEN(num_dma_symbol_total_rden3),
.RST(!rstn),
.WREN(num_dma_symbol_total_wren3),
.data_count(num_dma_symbol_fifo_data_count3)
);

State machines

  • state machine to do tx for high layer if high_tx_allowed
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