Entity: tx_control

• File: tx_control.v

Diagram

Description

Generics

Generic name	Type	Value	Description
RSSI_HALF_DB_WIDTH	integer	11
C_S00_AXIS_TDATA_WIDTH	integer	64
WIFI_TX_BRAM_ADDR_WIDTH	integer	10

Ports

Port name	Direction	Type	Description
clk	input	wire	main function: after receive data, send ack; after send data, disable tx for a while because need to wait for ack from peer.
rstn	input	wire
ack_disable	input	wire
preamble_sig_time	input	wire [6:0]
ofdm_symbol_time	input	wire [4:0]
sifs_time	input	wire [6:0]
max_num_retrans	input	wire [3:0]
tx_pkt_need_ack	input	wire
tx_pkt_retrans_limit	input	wire [3:0]
send_ack_wait_top	input	wire [14:0]	0 means 2.4GHz, non-zeros means 5GHz
recv_ack_timeout_top_adj	input	wire [14:0]
recv_ack_sig_valid_timeout_top	input	wire [14:0]
recv_ack_fcs_valid_disable	input	wire
pulse_tx_bb_end	input	wire
phy_tx_done	input	wire
sig_valid	input	wire
signal_rate	input	wire [7:0]
signal_len	input	wire [15:0]
fcs_valid	input	wire
fcs_in_strobe	input	wire
FC_type	input	wire [1:0]
FC_subtype	input	wire [3:0]
FC_more_frag	input	wire
cts_torts_disable	input	wire
cts_torts_rate	input	wire [4:0]
duration_extra	input	wire [15:0]
duration	input	wire [15:0]
addr2	input	wire [47:0]
self_mac_addr	input	wire [47:0]
addr1	input	wire [47:0]
douta	input	wire [63:0]
cts_toself_bb_is_ongoing	input	wire	this should rise before the phy tx end valid of phy tx IP core.
backoff_done	input	wire
bram_addr	input	wire [(WIFI_TX_BRAM_ADDR_WIDTH-1):0]
tx_control_state_idle	output	wire
ack_cts_is_ongoing	output	wire
retrans_in_progress	output
start_retrans	output
quit_retrans	input	wire
start_tx_ack	input
retrans_trigger	output
tx_try_complete	output
tx_status	output	[4:0]
ack_tx_flag	output
wea	output
addra	output	[9:0]
dina	output	[(C_S00_AXIS_TDATA_WIDTH-1):0]

Signals

Name	Type	Description
retrans_limit	wire [3:0]
num_retrans	reg [3:0]
ack_timeout_count	reg [14:0]
send_ack_count	reg [2:0]
ack_addr	reg [47:0]
duration_received	reg [15:0]
FC_more_frag_received	reg
tx_control_state	reg [2:0]
tx_fail_lock	reg
num_retrans_lock	reg [3:0]
is_data	wire	reg [2:0] tx_control_state_priv;
is_management	wire
is_blockackreq	wire
is_blockack	wire
is_pspoll	wire
is_rts	wire
ackcts_rate	reg [3:0]
ackcts_signal_parity	wire
ackcts_signal_len	wire [11:0]
douta_reg	reg [63:0]
tx_dpram_op_counter	reg [1:0]
num_data_ofdm_symbol_reg_tmp	reg [14:0]	`DEBUG_PREFIX wire [2:0] num_data_ofdm_symbol; reg [2:0] num_data_ofdm_symbol_reg;
ackcts_time	reg [7:0]
sifs_time_reg	reg [6:0]
recv_ack_timeout_top	reg [14:0]
duration_new	reg [15:0]
FC_type_new	reg [1:0]
FC_subtype_new	reg [3:0]
is_data_received	reg
is_management_received	reg
is_blockackreq_received	reg
is_blockack_received	reg
is_pspoll_received	reg
is_rts_received	reg
send_ack_wait_top_scale	reg [14:0]
recv_ack_sig_valid_timeout_top_scale	reg [14:0]
recv_ack_timeout_top_adj_scale	reg [14:0]
retrans_started	reg

Constants

Name	Type	Value	Description
IDLE	[2:0]	3'b000
SEND_ACK	[2:0]	3'b001
SEND_ACK_DO	[2:0]	3'b010
RECV_ACK_JUDGE	[2:0]	3'b011
RECV_ACK_WAIT_TX_BB_DONE	[2:0]	3'b100
RECV_ACK_WAIT_SIG_VALID	[2:0]	3'b101
RECV_ACK	[2:0]	3'b110
RECV_ACK_WAIT_BACKOFF_DONE	[2:0]	3'b111

Processes

• unnamed: ( @(posedge clk) )

State machines