Entity: ad9767

Diagram

dac_clk_i dac_2clk_i dac_2ph_i dac_locked_i dac_dat_a_en_i dac_dat_a_rst_i [ 14-1: 0] dac_dat_a_i dac_dat_b_en_i dac_dat_b_rst_i [ 14-1: 0] dac_dat_b_i [ 14-1: 0] dac_dat_o dac_wrt_o dac_sel_o dac_clk_o dac_rst_o

Ports

Port name Direction Type Description
dac_clk_i input DAC clks
dac_2clk_i input
dac_2ph_i input
dac_locked_i input
dac_dat_o output [ 14-1: 0] !< DAC IC combined data
dac_wrt_o output !< DAC IC write enable
dac_sel_o output !< DAC IC channel select
dac_clk_o output !< DAC IC clock
dac_rst_o output !< DAC IC reset
dac_dat_a_en_i input
dac_dat_a_rst_i input
dac_dat_a_i input [ 14-1: 0] !< DAC CHA data
dac_dat_b_en_i input
dac_dat_b_rst_i input
dac_dat_b_i input [ 14-1: 0] !< DAC CHB data

Signals

Name Type Description
dac_rst reg
dac_dat_a reg [14-1: 0] ---------------------------------------------------------------------------------
Fast DAC - DDR interface
dac_dat_b reg [14-1: 0]
dac_dat_a_s reg [14-1: 0]
dac_dat_b_s reg [14-1: 0]

Processes

Type: always

Type: always

Description
output registers + signed to unsigned (also to negative slope)

Instantiations