Entity: add_constReal_logic

Diagram

string format natural DATA_OUT_SIZE natural DATA_IN_SIZE std_logic rst_i std_logic clk_i std_logic_vector(DATA_IN_SIZE-1 downto 0) add_val std_logic_vector(DATA_IN_SIZE-1 downto 0) data_i std_logic data_en_i std_logic_vector(DATA_OUT_SIZE-1 downto 0) data_o std_logic data_en_o

Generics

Generic name Type Value Description
format string "signed"
DATA_OUT_SIZE natural 18
DATA_IN_SIZE natural 16

Ports

Port name Direction Type Description
rst_i in std_logic Syscon signals
clk_i in std_logic
add_val in std_logic_vector(DATA_IN_SIZE-1 downto 0) config
data_i in std_logic_vector(DATA_IN_SIZE-1 downto 0) input data
data_en_i in std_logic
data_o out std_logic_vector(DATA_OUT_SIZE-1 downto 0) for the next component
data_en_o out std_logic

Signals

Name Type Description
data_in_s std_logic_vector(DATA_OUT_SIZE-1 downto 0)
data_s std_logic_vector(DATA_OUT_SIZE-1 downto 0)

Processes