Entity: check_valid_burst

Diagram

natural ACCUM_SIZE natural DATA_SIZE natural ADDR_SIZE natural DFLT_START_OFFSET natural DFLT_STOP_OFFSET natural DFLT_LIMIT natural id integer C_S00_AXI_DATA_WIDTH integer C_S00_AXI_ADDR_WIDTH std_logic s00_axi_aclk std_logic s00_axi_reset std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0) s00_axi_awaddr std_logic s00_axi_awvalid std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0) s00_axi_wdata std_logic s00_axi_wvalid std_logic s00_axi_bready std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0) s00_axi_araddr std_logic s00_axi_arvalid std_logic s00_axi_rready std_logic data_en_i std_logic data_eof_i std_logic data_clk_i std_logic data_rst_i std_logic_vector(DATA_SIZE-1 downto 0) data_i_i std_logic_vector(DATA_SIZE-1 downto 0) data_q_i std_logic s00_axi_awready std_logic s00_axi_wready std_logic_vector(1 downto 0) s00_axi_bresp std_logic s00_axi_bvalid std_logic s00_axi_arready std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0) s00_axi_rdata std_logic_vector(1 downto 0) s00_axi_rresp std_logic s00_axi_rvalid std_logic data_en_o std_logic data_eof_o std_logic data_clk_o std_logic data_rst_o std_logic_vector(DATA_SIZE-1 downto 0) data_i_o std_logic_vector(DATA_SIZE-1 downto 0) data_q_o

Description

warning !!!! -------------------- cpt_max_val is the last value -- allowed (ie the addr) -- consequently for 2048 sample the-- last value is 2047 since 0 is --

an valid offset --

Generics

Generic name Type Value Description
ACCUM_SIZE natural 32
DATA_SIZE natural 14
ADDR_SIZE natural 10
DFLT_START_OFFSET natural 500
DFLT_STOP_OFFSET natural 1024
DFLT_LIMIT natural 10000
id natural 1
C_S00_AXI_DATA_WIDTH integer 32 Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_ADDR_WIDTH integer 4

Ports

Port name Direction Type Description
s00_axi_aclk in std_logic
s00_axi_reset in std_logic
s00_axi_awaddr in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0) Wishbone signals
s00_axi_awvalid in std_logic 00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awready out std_logic
s00_axi_wdata in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0)
s00_axi_wvalid in std_logic 00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wready out std_logic
s00_axi_bresp out std_logic_vector(1 downto 0)
s00_axi_bvalid out std_logic
s00_axi_bready in std_logic
s00_axi_araddr in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0)
s00_axi_arvalid in std_logic 00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arready out std_logic
s00_axi_rdata out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0)
s00_axi_rresp out std_logic_vector(1 downto 0)
s00_axi_rvalid out std_logic
s00_axi_rready in std_logic
data_en_i in std_logic
data_eof_i in std_logic
data_clk_i in std_logic
data_rst_i in std_logic
data_i_i in std_logic_vector(DATA_SIZE-1 downto 0)
data_q_i in std_logic_vector(DATA_SIZE-1 downto 0)
data_en_o out std_logic
data_eof_o out std_logic
data_clk_o out std_logic
data_rst_o out std_logic
data_i_o out std_logic_vector(DATA_SIZE-1 downto 0)
data_q_o out std_logic_vector(DATA_SIZE-1 downto 0)

Signals

Name Type Description
start_mean_offset_s std_logic_vector(ADDR_SIZE-1 downto 0)
max_allowed_val_s std_logic_vector(ACCUM_SIZE-1 downto 0)
cpt_max_s std_logic_vector(ADDR_SIZE-1 downto 0)
addr_s std_logic_vector(1 downto 0) comm
write_en_s std_logic
read_en_s std_logic

Instantiations

Description
data_i_o <= data_i_i;
data_q_o <= data_q_i;
data_eof_o <= data_eof_i;
data_en_o <= data_en_i;