Entity: dupplReal_1_to_2

Diagram

natural DATA_SIZE std_logic data_en_i std_logic data_eof_i std_logic data_clk_i std_logic data_rst_i std_logic_vector(DATA_SIZE-1 downto 0) data_i std_logic data1_en_o std_logic data1_eof_o std_logic data1_clk_o std_logic data1_rst_o std_logic_vector(DATA_SIZE-1 downto 0) data1_o std_logic data2_en_o std_logic data2_eof_o std_logic data2_clk_o std_logic data2_rst_o std_logic_vector(DATA_SIZE-1 downto 0) data2_o

Description

(c) Copyright: OscillatorIMP Digital Author : Gwenhael Goavec-Merougwenhael.goavec-merou@trabucayre.com

Creation date : 2014/10/14

Generics

Generic name Type Value Description
DATA_SIZE natural 8

Ports

Port name Direction Type Description
data_en_i in std_logic DATA in
data_eof_i in std_logic
data_clk_i in std_logic
data_rst_i in std_logic
data_i in std_logic_vector(DATA_SIZE-1 downto 0)
data1_en_o out std_logic next
data1_eof_o out std_logic
data1_clk_o out std_logic
data1_rst_o out std_logic
data1_o out std_logic_vector(DATA_SIZE-1 downto 0)
data2_en_o out std_logic
data2_eof_o out std_logic
data2_clk_o out std_logic
data2_rst_o out std_logic
data2_o out std_logic_vector(DATA_SIZE-1 downto 0)