Expander Complex

Diagram

string format natural DATA_IN_SIZE natural DATA_OUT_SIZE std_logic_vector(DATA_IN_SIZE-1 downto 0) data_i_i std_logic_vector(DATA_IN_SIZE-1 downto 0) data_q_i std_logic data_en_i std_logic data_sof_i std_logic data_eof_i std_logic data_rst_i std_logic data_clk_i std_logic_vector(DATA_OUT_SIZE-1 downto 0) data_i_o std_logic_vector(DATA_OUT_SIZE-1 downto 0) data_q_o std_logic data_en_o std_logic data_sof_o std_logic data_eof_o std_logic data_rst_o std_logic data_clk_o

Description

Generics

Generic name Type Value Description
format string "signed" tell if stream is signed or unsigned
DATA_IN_SIZE natural 16 size of the input data stream
DATA_OUT_SIZE natural 16 size of the output data stream

Ports

Port name Direction Type Description
data_i_i in std_logic_vector(DATA_IN_SIZE-1 downto 0) input data
data_q_i in std_logic_vector(DATA_IN_SIZE-1 downto 0)
data_en_i in std_logic
data_sof_i in std_logic
data_eof_i in std_logic
data_rst_i in std_logic
data_clk_i in std_logic
data_i_o out std_logic_vector(DATA_OUT_SIZE-1 downto 0) for the next component
data_q_o out std_logic_vector(DATA_OUT_SIZE-1 downto 0)
data_en_o out std_logic
data_sof_o out std_logic
data_eof_o out std_logic
data_rst_o out std_logic
data_clk_o out std_logic

Signals

Name Type Description
msb_i_s std_logic_vector(MSB_SIZE-1 downto 0) dropped part of the I input signal
msb_q_s std_logic_vector(MSB_SIZE-1 downto 0) dropped part of the Q input signal
is_zero_i boolean check is high slice is fully 0 and 1
is_one_i boolean check is high slice is fully 0 and 1
is_zero_q boolean check is high slice is fully 0 and 1
is_one_q boolean check is high slice is fully 0 and 1

Constants

Name Type Value Description
MSB_SIZE natural comp_unused_slice(DATA_IN_SIZE,
DATA_OUT_SIZE)		 size of the dropped part of input signal

Functions