Entity: gen_radar_prog

Diagram

natural ID integer C_S00_AXI_DATA_WIDTH integer C_S00_AXI_ADDR_WIDTH natural DATA_SIZE natural BURST_SIZE natural RXOFF natural TXON std_logic_vector(DATA_SIZE-1 downto 0) data_i_i std_logic_vector(DATA_SIZE-1 downto 0) data_q_i std_logic data_en_i std_logic data_clk_i std_logic data_rst_i std_logic s00_axi_aclk std_logic s00_axi_reset std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0) s00_axi_awaddr std_logic_vector(2 downto 0) s00_axi_awprot std_logic s00_axi_awvalid std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0) s00_axi_wdata std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0) s00_axi_wstrb std_logic s00_axi_wvalid std_logic s00_axi_bready std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0) s00_axi_araddr std_logic_vector(2 downto 0) s00_axi_arprot std_logic s00_axi_arvalid std_logic s00_axi_rready std_logic switch_o std_logic switchn_o std_logic_vector(DATA_SIZE-1 downto 0) data_i_o std_logic_vector(DATA_SIZE-1 downto 0) data_q_o std_logic data_en_o std_logic data_clk_o std_logic data_rst_o std_logic data_eof_o std_logic s00_axi_awready std_logic s00_axi_wready std_logic_vector(1 downto 0) s00_axi_bresp std_logic s00_axi_bvalid std_logic s00_axi_arready std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0) s00_axi_rdata std_logic_vector(1 downto 0) s00_axi_rresp std_logic s00_axi_rvalid

Description

(c) Copyright: OscillatorIMP Digital Author : Gwenhael Goavec-Merougwenhael.goavec-merou@trabucayre.com

2013-2018

Generics

Generic name Type Value Description
ID natural 1
C_S00_AXI_DATA_WIDTH integer 32
C_S00_AXI_ADDR_WIDTH integer 4
DATA_SIZE natural 16 req_in : natural := 200; -- ADC clock rate en MHz
BURST_SIZE natural 1024
RXOFF natural 2 exprime' en cycle
TXON natural 8 idem

Ports

Port name Direction Type Description
switch_o out std_logic Syscon signals
switchn_o out std_logic
data_i_i in std_logic_vector(DATA_SIZE-1 downto 0) rocessing
data_q_i in std_logic_vector(DATA_SIZE-1 downto 0)
data_en_i in std_logic
data_clk_i in std_logic
data_rst_i in std_logic
data_i_o out std_logic_vector(DATA_SIZE-1 downto 0)
data_q_o out std_logic_vector(DATA_SIZE-1 downto 0)
data_en_o out std_logic
data_clk_o out std_logic
data_rst_o out std_logic
data_eof_o out std_logic
s00_axi_aclk in std_logic axi
s00_axi_reset in std_logic
s00_axi_awaddr in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0)
s00_axi_awprot in std_logic_vector(2 downto 0)
s00_axi_awvalid in std_logic
s00_axi_awready out std_logic
s00_axi_wdata in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0)
s00_axi_wstrb in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0)
s00_axi_wvalid in std_logic
s00_axi_wready out std_logic
s00_axi_bresp out std_logic_vector(1 downto 0)
s00_axi_bvalid out std_logic
s00_axi_bready in std_logic
s00_axi_araddr in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0)
s00_axi_arprot in std_logic_vector(2 downto 0)
s00_axi_arvalid in std_logic
s00_axi_arready out std_logic
s00_axi_rdata out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0)
s00_axi_rresp out std_logic_vector(1 downto 0)
s00_axi_rvalid out std_logic
s00_axi_rready in std_logic

Signals

Name Type Description
rxoff_s std_logic_vector(15 downto 0)
txon_s std_logic_vector(15 downto 0)
addr_s std_logic_vector(1 downto 0)
write_en_s std_logic
read_en_s std_logic
point_period_s std_logic_vector(15 downto 0)

Instantiations

Description
Instantiation of Axi Bus Interface S00_AXI