Entity: pl330_dma_fifo

Diagram

integer RAM_ADDR_WIDTH integer FIFO_DWIDTH integer FIFO_DIRECTION std_logic clk std_logic resetn std_logic fifo_reset Boolean enable std_logic in_stb std_logic_vector(FIFO_DWIDTH-1 downto 0) in_data std_logic out_ack std_logic dclk std_logic dresetn std_logic davalid std_logic_vector(1 downto 0) datype std_logic drready std_logic in_ack std_logic out_stb std_logic_vector(FIFO_DWIDTH-1 downto 0) out_data_left std_logic_vector(FIFO_DWIDTH-1 downto 0) out_data_right std_logic daready std_logic drvalid std_logic_vector(1 downto 0) drtype std_logic drlast

Description

Copyright 2019 (c) OscillatorIMP Digital Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.

The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.

This core is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Redistribution and use of source or resulting binaries, with or without modification of this file, are permitted under one of the following two license terms:

  1. The GNU General Public License version 2 as published by the Free Software Foundation, which can be found in the top level directory of this repository (LICENSE_GPL2), and also online at: https://www.gnu.org/licenses/old-licenses/gpl-2.0.html

OR

  1. An ADI specific BSD license, which can be found in the top level directory of this repository (LICENSE_ADIBSD), and also on-line at: https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD This will allow to generate bit files and not release the source code, as long as it attaches to an ADI device.

Generics

Generic name Type Value Description
RAM_ADDR_WIDTH integer 3
FIFO_DWIDTH integer 32
FIFO_DIRECTION integer 0 0 = write FIFO, 1 = read FIFO

Ports

Port name Direction Type Description
clk in std_logic
resetn in std_logic
fifo_reset in std_logic
enable in Boolean Enable DMA interface
in_stb in std_logic Write port
in_ack out std_logic
in_data in std_logic_vector(FIFO_DWIDTH-1 downto 0)
out_stb out std_logic Read port
out_ack in std_logic
out_data_left out std_logic_vector(FIFO_DWIDTH-1 downto 0)
out_data_right out std_logic_vector(FIFO_DWIDTH-1 downto 0)
dclk in std_logic PL330 DMA interface
dresetn in std_logic
davalid in std_logic
daready out std_logic
datype in std_logic_vector(1 downto 0)
drvalid out std_logic
drready in std_logic
drtype out std_logic_vector(1 downto 0)
drlast out std_logic

Signals

Name Type Description
request_data Boolean
state state_type
i_in_ack std_logic
i_out_stb std_logic

Types

Name Type Description
state_type (IDLE,
REQUEST,
WAITING,
FLUSH)

Processes

Instantiations

State machines

state transitions cluster_state state IDLE IDLE REQUEST REQUEST IDLE->REQUEST request_data and enable    WAITING WAITING REQUEST->WAITING drready = '1'    WAITING->IDLE fifo_reset = '1'    WAITING->IDLE datype = "00"    davalid = '1'    FLUSH FLUSH FLUSH->IDLE drready = '1'