Entity: prn20b

Diagram

natural DFLT_PRESC natural PRESC_SIZE integer C_S00_AXI_DATA_WIDTH integer C_S00_AXI_ADDR_WIDTH std_logic s00_axi_aclk std_logic s00_axi_reset std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0) s00_axi_awaddr std_logic_vector(2 downto 0) s00_axi_awprot std_logic s00_axi_awvalid std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0) s00_axi_wdata std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0) s00_axi_wstrb std_logic s00_axi_wvalid std_logic s00_axi_bready std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0) s00_axi_araddr std_logic_vector(2 downto 0) s00_axi_arprot std_logic s00_axi_arvalid std_logic s00_axi_rready std_logic ref_clk_i std_logic ref_rst_i std_logic s00_axi_awready std_logic s00_axi_wready std_logic_vector(1 downto 0) s00_axi_bresp std_logic s00_axi_bvalid std_logic s00_axi_arready std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0) s00_axi_rdata std_logic_vector(1 downto 0) s00_axi_rresp std_logic s00_axi_rvalid std_logic_vector(19 downto 0) prn_full_o std_logic prn_full_en_o std_logic prn_full_clk_o std_logic prn_full_rst_o std_logic test_o std_logic bit_o

Description

(c) Copyright: OscillatorIMP Digital Author : Gwenhael Goavec-Merougwenhael.goavec-merou@trabucayre.com

Creation date : 2018/06/11

Generics

Generic name Type Value Description
DFLT_PRESC natural 15
PRESC_SIZE natural 16
C_S00_AXI_DATA_WIDTH integer 32 Parameters of Axi Slave Bus Interface S00_AXI
C_S00_AXI_ADDR_WIDTH integer 3

Ports

Port name Direction Type Description
s00_axi_aclk in std_logic Ports of Axi Lite Slave Bus Interface S00_AXI
s00_axi_reset in std_logic
s00_axi_awaddr in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0)
s00_axi_awprot in std_logic_vector(2 downto 0)
s00_axi_awvalid in std_logic
s00_axi_awready out std_logic
s00_axi_wdata in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0)
s00_axi_wstrb in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0)
s00_axi_wvalid in std_logic
s00_axi_wready out std_logic
s00_axi_bresp out std_logic_vector(1 downto 0)
s00_axi_bvalid out std_logic
s00_axi_bready in std_logic
s00_axi_araddr in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0)
s00_axi_arprot in std_logic_vector(2 downto 0)
s00_axi_arvalid in std_logic
s00_axi_arready out std_logic
s00_axi_rdata out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0)
s00_axi_rresp out std_logic_vector(1 downto 0)
s00_axi_rvalid out std_logic
s00_axi_rready in std_logic
ref_clk_i in std_logic specific signals
ref_rst_i in std_logic
prn_full_o out std_logic_vector(19 downto 0)
prn_full_en_o out std_logic
prn_full_clk_o out std_logic
prn_full_rst_o out std_logic
test_o out std_logic
bit_o out std_logic

Signals

Name Type Description
addr_s std_logic_vector(INTERNAL_ADDR_WIDTH-1 downto 0)
write_en_s std_logic
read_en_s std_logic
prescaler_s std_logic_vector(PRESC_SIZE-1 downto 0)
presc_sync_s std_logic_vector(PRESC_SIZE-1 downto 0)
tick_s std_logic
test_s std_logic

Constants

Name Type Value Description
INTERNAL_ADDR_WIDTH natural 1

Processes

Instantiations

Description
Instantiation of Axi Bus Interface S00_AXI