Entity: top_cacode_tb
- File: top_cacode_tb.vhd
Diagram
Signals
| Name | Type | Description |
|---|---|---|
| reset | std_logic | |
| clk | std_logic | |
| g1_s | std_logic | |
| g2_s | std_logic | |
| g1_full_s | std_logic_vector(9 downto 0) | |
| cacode_s | std_logic_vector(9 downto 0) | |
| clk_gen_s | std_logic | |
| tick_s | std_logic | |
| truc_s | data_tab(31 downto 0) | |
| gold_code_s | std_logic_vector(31 downto 0) |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| HALF_PERIOD | time | 5.0 ns | Half clock period |
Types
| Name | Type | Description |
|---|---|---|
| data_tab | array (natural range <>) of std_logic_vector(9 downto 0) |
Processes
- stimulis: ( )
- store_result: ( clk, reset )
- clockp: ( )
Instantiations
- cacode1_inst: work.cacode