Entity: top_cvb_tb

Diagram

Description

use work.sp_vision_test_pkg.all;

Signals

Name Type Description
reset std_logic
clk std_logic
start_mean_offset_s std_logic_vector(ADDR_SIZE-1 downto 0) config --
max_allowed_val_s std_logic_vector(ACCUM_SIZE-1 downto 0)
cpt_max_s std_logic_vector(ADDR_SIZE-1 downto 0)
write_i_s std_logic_vector(DATA_SIZE-1 downto 0) write from file to RAM --
write_q_s std_logic_vector(DATA_SIZE-1 downto 0) write from file to RAM --
write_addr_s std_logic_vector(RAM_ADDR_SIZE-1 downto 0)
write_en_s std_logic
write_end_s std_logic
start_read_s std_logic read for flow generation --
read_i_s std_logic_vector(DATA_SIZE-1 downto 0)
read_q_s std_logic_vector(DATA_SIZE-1 downto 0)
read_addr_s std_logic_vector(RAM_ADDR_SIZE-1 downto 0)
read_en_s std_logic
read_end_s std_logic
data_i_s std_logic_vector(DATA_SIZE-1 downto 0) input --
data_q_s std_logic_vector(DATA_SIZE-1 downto 0)
data_en_s std_logic
data_eof_s std_logic
result_i_s std_logic_vector(DATA_SIZE-1 downto 0) output --
result_q_s std_logic_vector(DATA_SIZE-1 downto 0)
result_en_s std_logic
result_eof_s std_logic
generate_en_s std_logic --misc
cpt_s std_logic_vector(ADDR_SIZE-1 downto 0)
cpt2_s std_logic_vector(2 downto 0)
wait_a_bit std_logic

Constants

Name Type Value Description
HALF_PERIODE time 5.0 ns Half clock period
ADDR_SIZE natural 10
DATA_SIZE natural 16
ACCUM_SIZE natural 32
RAM_ADDR_SIZE natural ADDR_SIZE + 3

Functions

Processes

Instantiations

Description
start_mean_offset_s <= (ADDR_SIZE-1 downto 3 => '0') & (2 downto 0 => '1');
max_allowed_val_s <= (ACCUM_SIZE-1 downto 4 => '0') & (3 downto 0 => '1');
cpt_max_s <= (ADDR_SIZE-1 downto 4 => '0') & (3 downto 0 => '1');

Description
-- read coeff for fir16 LUT