Entity: top_data_subtop_tb

• File: top_data_subtop_tb.vhd

Diagram

Description

Signals

Name	Type	Description
reset	std_logic
clk	std_logic
start_prod_s	std_logic	data gen
busy_s	std_logic
result_s	std_logic_vector(AXI_SIZE-1 downto 0)
read_i_s	std_logic_vector(15 downto 0)
read_q_s	std_logic_vector(15 downto 0)
result_addr_s	std_logic_vector(ADDR_SIZE-1 downto 0)
data_i_s	std_logic_vector(15 downto 0)
wr_i_s	std_logic_vector(DATA_SIZE-1 downto 0)
wr_q_s	std_logic_vector(DATA_SIZE-1 downto 0)
data_en_s	std_logic
state_s	std_logic
state_read_s	read_state
data_next_s	std_logic_vector(AXI_SIZE-1 downto 0)
data_next_en_s	std_logic

Constants

Name	Type	Value	Description
HALF_PERIODE	time	5.0 ns	Half clock period
DATA_SIZE	natural	32
ADDR_SIZE	natural	6
AXI_SIZE	natural	32

Types

Name	Type	Description
read_state	(IDLE, WAIT_END, READ, WAIT1, WAIT2)

Processes

• unnamed: ( clk )

• unnamed: ( clk )

• stimulis: ( )

• clockp: ( )

Instantiations

• dut: work.dataComplex_to_ram_subtop

State machines