Entity: top_delayTempo_tb
- File: top_delayTempo_tb.vhd
Diagram
Signals
| Name | Type | Description |
|---|---|---|
| reset | std_logic | |
| clk | std_logic | |
| data_in_s | std_logic_vector(DATA_SIZE-1 downto 0) | new |
| data_out_s | std_logic_vector(DATA_SIZE-1 downto 0) | new |
| data_in_en_s | std_logic | |
| data_out_en_s | std_logic | |
| start_prod | std_logic | |
| cpt_s | natural range 0 to MAX_CNT-1 | |
| delay_s | std_logic_vector(DELAY_ADDR_SZ-1 downto 0) |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| DATA_SIZE | natural | 14 | |
| HALF_PERIODE | time | 5.0 ns | Half clock period |
| SL_MAX | natural | 1 | output result from fir |
| MAX_CNT | natural | 6 | |
| MAX_NB_DELAY | natural | 10 | |
| DELAY_ADDR_SZ | natural | natural(ceil(log2(real(MAX_NB_DELAY)))) |
Processes
- data_propagation: ( clk, reset )
Description
generate data flow
- stimulis: ( )
- clockp: ( )
Instantiations
- delay_inst: work.delayTempoReal_axi_logic