Entity: top_dma_fifo_tb

• File: top_dma_fifo_tb.vhd

Diagram

Signals

Name	Type	Description
reset	std_logic
rstn	std_logic
clk	std_logic
start_prod_s	std_logic
fifo_rst	std_logic
fifo_in_stb_s	std_logic
fifo_in_ack_s	std_logic
fifo_in_data_s	std_logic_vector(31 downto 0)
fifo_out_stb_s	std_logic
fifo_out_ack_s	std_logic
fifo_out_data_left_s	std_logic_vector(31 downto 0)
fifo_out_data_right_s	std_logic_vector(31 downto 0)
data_right_s	std_logic_vector(31 downto 0)
data_left_s	std_logic_vector(31 downto 0)

Constants

Name	Type	Value	Description
HALF_PERIODE	time	5.0 ns	Half clock period

Processes

• unnamed: ( clk )

• unnamed: ( clk )

• stimulis: ( )

• clockp: ( )

Instantiations

• dma_fifo_inst: work.dma_fifo