Entity: top_enable_tb
- File: top_enable_tb.vhd
Diagram
Description
use work.sp_vision_test_pkg.all;
Signals
| Name | Type | Description |
|---|---|---|
| reset | std_logic | |
| clk | std_logic | |
| adc_clk | std_logic | |
| data_en_s | std_logic | new |
| data_i_s | std_logic_vector(15 downto 0) | |
| data_q_s | std_logic_vector(15 downto 0) | |
| result_i_s | std_logic_vector(15 downto 0) | output result from fir |
| result_q_s | std_logic_vector(15 downto 0) | output result from fir |
| result_en_s | std_logic | |
| result_eof_s | std_logic | |
| result2_i_s | std_logic_vector(15 downto 0) | |
| result2_q_s | std_logic_vector(15 downto 0) | |
| result2_en_s | std_logic | |
| switch_s | std_logic | |
| switchn_s | std_logic |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| HALF_PERIODE | time | 5.0 ns | Half clock period |
| ADC_PERIOD | time | 2.5 ns | Half clock period |
Processes
- data_propagation: ( adc_clk, reset )
Description
point_inst: Entity work.extract_data_from_rafale generic map ( DATA_SIZE => 16, POINT_POS => 8 ) port map ( -- Syscon signals reset => reset, clk => adc_clk, -- input data data_i_i => result_i_s, data_q_i => result_q_s, data_eof_i => result_eof_s, data_en_i => result_en_s, -- for the next component data_q_o => result2_q_s, data_i_o => result2_i_s, data_en_o => result2_en_s ); generate data flow
- stimulis: ( )
- clockp: ( )
- clockadc: ( )
Instantiations
- generateur: work.gen_radar_prog_logic