Entity: top_mean_vector_tb

• File: top_mean_vector_tb.vhd

Diagram

Description

Signals

Name	Type	Description
reset	std_logic
clk	std_logic
data_in_en_s	std_logic
data_out_en_s	std_logic
data_in_eof_s	std_logic
data_out_eof_s	std_logic
data_in_i_s	std_logic_vector(DATA_SIZE-1 downto 0)
data_in_q_s	std_logic_vector(DATA_SIZE-1 downto 0)
data_out_i_s	std_logic_vector(DATA_SIZE-1 downto 0)
data_out_q_s	std_logic_vector(DATA_SIZE-1 downto 0)
start_prod	std_logic
cpt_s	natural range 0 to FRAME_LENGTH-1
cpt2_s	natural range 0 to UPDATE_LENGTH-1
nb_iter_s	std_logic_vector(ACCUM_SIZE-1 downto 0)
nb_iter_sync_s	std_logic_vector(ACCUM_SIZE-1 downto 0)
shift_val_s	std_logic_vector(SHIFT_SIZE-1 downto 0)
shift_val_sync_s	std_logic_vector(SHIFT_SIZE-1 downto 0)

Constants

Name	Type	Value	Description
DATA_SIZE	natural	32
FRAME_LENGTH	natural	8
UPDATE_LENGTH	natural	60
HALF_PERIODE	time	5.0 ns	Half clock period
SIM_ITER	natural	1
SIM_SHIFT	natural	0
MAX_NB_ACCUM	natural	32
ACCUM_SIZE	natural	natural(ceil(log2(real(MAX_NB_ACCUM))))	2^ACCUM_SIZE => NB_ACCUM (in fact 0 -> NB_ACCUM-1 but …)
SHIFT_SIZE	natural	natural(ceil(log2(real(ACCUM_SIZE))))	we need to describe the shift size divide by 1024 is >> 10 => 10 must be used with 2^4 = 16

Processes

• data_propagation: ( clk, reset )

• stimulis: ( )

• clockp: ( )

Instantiations

• mult_const_inst: work.mean_vector_axi_logic