Entity: top_nco_counter_tb

Diagram

Signals

Name Type Description
reset std_logic
clk std_logic
cpt_step_s std_logic_vector(COUNTER_SIZE-1 downto 0)
cpt_tmp_s std_logic_vector(COUNTER_SIZE-1 downto 0)
reset_nco_s std_logic
cos_fake_s std_logic
sin_fake_s std_logic
wave_en_s std_logic
cos_s std_logic_vector(DATA_SIZE-1 downto 0)
sin_s std_logic_vector(DATA_SIZE-1 downto 0)
cos2_fake_s std_logic
sin2_fake_s std_logic
wave2_en_s std_logic
cos2_s std_logic_vector(DATA_SIZE-1 downto 0)
sin2_s std_logic_vector(DATA_SIZE-1 downto 0)
cos3_fake_s std_logic
sin3_fake_s std_logic
wave3_en_s std_logic
cos3_s std_logic_vector(DATA_SIZE-1 downto 0)
sin3_s std_logic_vector(DATA_SIZE-1 downto 0)
ready_store_s std_logic
max_accum_s std_logic_vector(COUNTER_SIZE-1 downto 0)

Constants

Name Type Value Description
LUT_SIZE natural 12
COUNTER_SIZE natural 32
DATA_SIZE natural 14
HALF_PERIODE time 4 ns 5.0 ns; -- Half clock period

Functions

Processes

Description
nco2_inst : entity work.nco_counter_logic generic map(LUT_SIZE => LUT_SIZE, TEST => true, COUNTER_SIZE => COUNTER_SIZE, DATA_SIZE => DATA_SIZE) port map(rst_i => reset, clk_i => clk, cpu_clk_i => '0', - cpt_off_i => (LUT_SIZE-1 downto 0 => '0'), cpt_step_i => cpt_tmp_s, test_o => open, cos_o => cos2_s, sin_o => sin2_s, cos_fake_o => cos2_fake_s, sin_fake_o => sin2_fake_s, wave_en_o => wave2_en_s ); nco3_inst : entity work.nco_counter_logic generic map(LUT_SIZE => 24, COUNTER_SIZE => COUNTER_SIZE, DATA_SIZE => DATA_SIZE) port map(rst_i => reset, clk_i => clk, cpu_clk_i => '0', cpt_off_i => (24 downto 0 => '0'), cpt_step_i => cpt_step_s, test_o => open, step_scale_o => open, cos_o => cos2_s, sin_o => sin2_s, cos_fake_o => cos2_fake_s, sin_fake_o => sin2_fake_s, wave_en_o => wave2_en_s );

Instantiations