Entity: top_shifterReal_dyn_tb

• File: top_shifterReal_dyn_tb.vhd

Diagram

Signals

Name	Type	Description
reset	std_logic
clk	std_logic
start_prod	std_logic
data_in_en_s	std_logic	new
data_out_en_s	std_logic	new
data_in_s	std_logic_vector(DATA_IN_SIZE-1 downto 0)
data_out_s	std_logic_vector(DATA_OUT_SIZE-1 downto 0)
state_s	std_logic
shift_val_s	std_logic_vector(ADDR_SIZE-1 downto 0)

Constants

Name	Type	Value	Description
DATA_IN_SIZE	natural	32
DATA_OUT_SIZE	natural	16
MAX_SHIFT	natural	DATA_IN_SIZE - DATA_OUT_SIZE + 1
ADDR_SIZE	natural	natural(ceil(log2(real(MAX_SHIFT))))
HALF_PERIODE	time	5.0 ns	Half clock period

Processes

• data_propagation: ( clk, reset )

• stimulis: ( )

• clockp: ( )

Instantiations

• shift_dyn_inst: work.shifterReal_dyn_logic