Entity: top_slv_to_sl_axi_tb
- File: top_slv_to_sl_axi_tb.vhd
Diagram
Signals
| Name | Type | Description |
|---|---|---|
| clk | std_logic | |
| reset | std_logic | |
| offset_s | std_logic_vector(OFFSET_ADDR_SZ-1 downto 0) | |
| sl_s | std_logic | |
| slv_s | std_logic_vector(SLV_SIZE-1 downto 0) |
Constants
| Name | Type | Value | Description |
|---|---|---|---|
| HALF_PERIOD | time | 5.0 ns | Half clock period |
| SLV_SIZE | natural | 32 | |
| OFFSET_ADDR_SZ | natural | natural(ceil(log2(real(SLV_SIZE)))) |
Processes
- stimulis: ( )
- clockp: ( )