Entity: top_windowReal_tb

• File: top_windowReal_tb.vhd

Diagram

Description

Signals

Name	Type	Description
reset	std_logic
clk	std_logic
coeff_s	std_logic_vector(COEFF_SIZE-1 downto 0)
coeff_addr_s	std_logic_vector(COEFF_ADDR_SIZE-1 downto 0)
coeff_en_s	std_logic
data_s	std_logic_vector(DATA_SIZE-1 downto 0)
data_en_s	std_logic
result_s	std_logic_vector(DATA_SIZE-1 downto 0)
result_en_s	std_logic
result_eof_s	std_logic
sl_clk_s	std_logic	misc
slow_clk	std_logic	misc
generate_en_s	std_logic
read_data_val_s	std_logic_vector(DATA_SIZE-1 downto 0)	ram for data
read_data_addr_s	std_logic_vector(10 downto 0)
read_data_en_s	std_logic
end_read_s	std_logic
prop_data_addr_s	std_logic_vector(10 downto 0)
tick_s	std_logic

Constants

Name	Type	Value	Description
HALF_PERIODE	time	5.0 ns	Half clock period
SLOW_PERIODE	time	10.0 ns	Half clock period
COEFF_ADDR_SIZE	natural	11
COEFF_SIZE	natural	21
SHIFT	natural	20
DATA_SIZE	natural	30
DATA_ADDR_SIZE	natural	11

Functions

• to_string (sv: std_logic_vector) return string

Processes

• unnamed: ( clk )

• stimulis: ( )

• clockp: ( )

• clk_divider: ( clk, reset )

• store_result: ( clk, reset )

Instantiations

• conv_inst: work.windowReal_logic

• read_coeff: work.readFromFile

• read_data_i: work.readFromFile

• ram_i: work.ram_storage16