Entity: windowReal_tb

• File: windowReal_tb.vhd

Diagram

Description

Signals

Name	Type	Description
reset	std_logic
clk	std_logic
adc_clk	std_logic
coeff_en_s	std_logic
coeff_val_s	std_logic_vector(15 downto 0)
coeff_addr_s	std_logic_vector(9 downto 0)
sl_clk_s	std_logic
slow_clk	std_logic
generate_en_s	std_logic
read_data_en_s	std_logic	data storage and propagation
read_data_val_s	std_logic_vector(15 downto 0)
read_data_addr_s	std_logic_vector(9 downto 0)
end_read_s	std_logic
end_read2_s	std_logic
prop_data_addr_s	std_logic_vector(9 downto 0)
prop_data_addr_nat_s	natural range 0 to 2**10-1
data_en_s	std_logic	new
data_s	std_logic_vector(15 downto 0)
result_s	std_logic_vector(31 downto 0)	output result from fir
result_en_s	std_logic
tick_s	std_logic
cpt_delay_s	natural range 0 to MAX_CNT-1

Constants

Name	Type	Value	Description
HALF_PERIODE	time	5.0 ns	Half clock period
ADC_PERIOD	time	2.5 ns	Half clock period
NB_FIR	natural	13
DECIMATE_FACTOR	natural	10
NB_COEFF	natural	128	constant NB_FIR : natural := 32; constant DECIMATE_FACTOR : natural := 4;
MAX_CNT	natural	100

Functions

• to_string (sv: Std_Logic_Vector) return string

Processes

• show_result: ( clk, reset )

• store_result: ( adc_clk, reset )

• unnamed: ( adc_clk, reset )

• data_propagation: ( adc_clk, reset )

• stimulis: ( )

• clockp: ( )

• clockadc: ( )

• clk_divider: ( clk, reset )

Instantiations

• fir16: work.firRealSlow_ng_top

• read_data: work.readFromFile

• ram_i: work.ram_storage16

• read_coeff: work.readFromFile