Entity: arith_inc_ovcy_xilinx

Diagram

positive N std_logic_vector(N-1 downto 0) p std_logic g std_logic v

Description

EMACS settings: -- tab-width: 2; indent-tabs-mode: t -- vim: tabstop=2:shiftwidth=2:noexpandtab

kate: tab-width 2; replace-tabs off; indent-width 2;

Authors: Thomas B. Preusser

Entity: TODO

Description:

.. TODO:: No documentation available.

============================================================================= Copyright 2007-2015 Technische Universität Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and

limitations under the License.

Generics

Generic name Type Value Description
N positive Bit Width

Ports

Port name Direction Type Description
p in std_logic_vector(N-1 downto 0) Argument
g in std_logic Increment Guard
v out std_logic Overflow Output

Signals

Name Type Description
c std_logic_vector(N downto 0)