Entity: arith_prefix_and

Diagram

positive N std_logic_vector(N-1 downto 0) x std_logic_vector(N-1 downto 0) y

Description

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Authors: Thomas B. Preusser Patrick Lehmann

Entity: Prefix AND computation

Description:

Prefix AND computation: y(i) <= '1' when x(i downto 0) = (i downto 0 => '1') else '0'; This implementation uses carry chains for wider implementations.

License:

Copyright 2007-2016 Technische Universität Dresden - Germany Chair of VLSI-Design, Diagnostics and Architecture

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and

limitations under the License.

Generics

Generic name Type Value Description
N positive

Ports

Port name Direction Type Description
x in std_logic_vector(N-1 downto 0)
y out std_logic_vector(N-1 downto 0)