Entity: arith_sqrt

Diagram

positive N std_logic rst std_logic clk std_logic_vector(N-1 downto 0) arg std_logic start std_logic_vector((N-1)/2 downto 0) sqrt std_logic rdy

Description

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Authors: Thomas B. Preußer

Entity: Iterative Square Root Extractor.

Description:

Iterative Square Root Extractor.

Its computation requires (N+1)/2 steps for an argument bit width of N.

License:

Copyright 2007-2014 Technische Universität Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and

limitations under the License.

Generics

Generic name Type Value Description
N positive := 8 -- Bit Width of Argument

Ports

Port name Direction Type Description
rst in std_logic Reset (synchronous)
clk in std_logic Clock
arg in std_logic_vector(N-1 downto 0) Radicand
start in std_logic Start Strobe
sqrt out std_logic_vector((N-1)/2 downto 0) Result
rdy out std_logic Ready / Done

Signals

Name Type Description
Rmd unsigned(N+STEPS-1 downto 0) Remainder / Result
Vld unsigned(STEPS-1 downto 0) Result Flags
Res unsigned(STEPS-1 downto 0) Extracted Result
diff unsigned(STEPS+1 downto 0) Tentative Difference

Constants

Name Type Value Description
STEPS positive (N+1)/2

Processes