Entity: arp_IPPool

Diagram

positive IPPOOL_SIZE T_NET_IPV4_ADDRESS_VECTOR INITIAL_IPV4ADDRESSES std_logic Clock std_logic Reset std_logic Lookup T_SLV_8 IPv4Address_Data std_logic IPv4Address_rst std_logic IPv4Address_nxt T_CACHE_RESULT PoolResult

Description

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kate: tab-width 2; replace-tabs off; indent-width 2;

Authors: Patrick Lehmann

Entity: TODO

Description:

.. TODO:: No documentation available.

License:

Copyright 2007-2015 Technische Universitaet Dresden - Germany Chair of VLSI-Design, Diagnostics and Architecture

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and

limitations under the License.

Generics

Generic name Type Value Description
IPPOOL_SIZE positive
INITIAL_IPV4ADDRESSES T_NET_IPV4_ADDRESS_VECTOR (0 to 7 => C_NET_IPV4_ADDRESS_EMPTY)

Ports

Port name Direction Type Description
Clock in std_logic
Reset in std_logic
Lookup in std_logic Command : in T_ETHERNET_ARP_IPPOOL_COMMAND; IPv4Address : in T_NET_IPV4_ADDRESS; MACAddress : in T_ETHERNET_MAC_ADDRESS;
IPv4Address_rst out std_logic
IPv4Address_nxt out std_logic
IPv4Address_Data in T_SLV_8
PoolResult out T_CACHE_RESULT

Signals

Name Type Description
ReadWrite std_logic
Insert std_logic
TU_NewTag_rst std_logic
TU_NewTag_nxt std_logic
NewTag_Data T_SLV_8
TU_Tag_rst std_logic
TU_Tag_nxt std_logic
TU_Tag_Data T_SLV_8
CacheHit std_logic
CacheMiss std_logic
TU_Index std_logic_vector(CACHEMEMORY_INDEX_BITS - 1 downto 0)
TU_Index_d std_logic_vector(CACHEMEMORY_INDEX_BITS - 1 downto 0)
TU_Index_us unsigned(CACHEMEMORY_INDEX_BITS - 1 downto 0)
TU_NewIndex std_logic_vector(CACHEMEMORY_INDEX_BITS - 1 downto 0)
TU_Replace std_logic
TU_TagHit std_logic
TU_TagMiss std_logic

Constants

Name Type Value Description
CACHE_LINES positive imax(IPPOOL_SIZE,
INITIAL_IPV4ADDRESSES'length)
TAG_BITS positive 32
TAGCHUNK_BITS positive 8
CACHEMEMORY_INDEX_BITS positive log2ceilnz(CACHE_LINES) constant TAGCHUNKS : POSITIVE := div_ceil(TAG_BITS, CHUNK_BITS); constant CHUNK_INDEX_BITS : POSITIVE := log2ceilnz(CHUNKS);
INITIAL_TAGS T_SLM to_TagData(INITIAL_IPV4ADDRESSES)

Functions

Instantiations

Description
Cache TagUnit
TU : entity PoC.Cache_TagUnit_seq