Package: components
- File: components.vhdl
Functions
- registered (signal Clock : std_logic;
constant IsRegistered : boolean) return boolean
- ffrs (q : std_logic;
rst : std_logic := '0';
set : std_logic := '0') return std_logic
Description
RS-FlipFlop with dominant rst
- ffsr (q : std_logic;
rst : std_logic := '0';
set : std_logic := '0') return std_logic
Description
RS-FlipFlop with dominant set
- ffdre (q : std_logic;
d : std_logic;
rst : std_logic := '0';
en : std_logic := '1';
constant INIT : std_logic := '0') return std_logic
Description
D-FlipFlop with reset and enable
- ffdre (q : std_logic_vector;
d : std_logic_vector;
rst : std_logic := '0';
en : std_logic := '1';
constant INIT : std_logic_vector := (0 to 0 => '0')) return std_logic_vector
Description
D-FlipFlop with reset and enable
- ffdse (q : std_logic;
d : std_logic;
set : std_logic := '0';
en : std_logic := '1') return std_logic
Description
D-FlipFlop with set and enable
- fftre (q : std_logic;
t : std_logic;
rst : std_logic := '0';
en : std_logic := '1';
constant INIT : std_logic := '0') return std_logic
Description
T-FlipFlop with reset and enable
- fftse (q : std_logic;
t : std_logic;
set : std_logic := '0';
en : std_logic := '1') return std_logic
Description
T-FlipFlop with set and enable
- upcounter_next (cnt : unsigned;
rst : std_logic := '0';
en : std_logic := '1';
constant INIT : natural := 0) return unsigned
Description
counter
- upcounter_equal (cnt : unsigned;
value : natural) return std_logic
- downcounter_next (cnt : signed;
rst : std_logic := '0';
en : std_logic := '1';
constant INIT : integer := 0) return signed
- downcounter_equal (cnt : signed;
value : integer) return std_logic
- downcounter_neg (cnt : signed) return std_logic
- shreg_left (q : std_logic_vector;
i : std_logic;
en : std_logic := '1') return std_logic_vector
Description
shiftregisters
- shreg_right (q : std_logic_vector;
i : std_logic;
en : std_logic := '1') return std_logic_vector
- rreg_left (q : std_logic_vector;
en : std_logic := '1') return std_logic_vector
Description
rotate registers
- rreg_right (q : std_logic_vector;
en : std_logic := '1') return std_logic_vector
- comp (value1 : std_logic_vector;
value2 : std_logic_vector) return std_logic_vector
Description
compare
- comp (value1 : unsigned;
value2 : unsigned) return unsigned
- comp (value1 : signed;
value2 : signed) return signed
- comp_allzero (value : std_logic_vector) return std_logic
- comp_allzero (value : unsigned) return std_logic
- comp_allzero (value : signed) return std_logic
- comp_allone (value : std_logic_vector) return std_logic
- comp_allone (value : unsigned) return std_logic
- comp_allone (value : signed) return std_logic
- mux (sel : std_logic;
sl0 : std_logic;
sl1 : std_logic) return std_logic
Description
multiplexing
- mux (sel : std_logic;
slv0 : std_logic_vector;
slv1 : std_logic_vector) return std_logic_vector
- mux (sel : std_logic;
us0 : unsigned;
us1 : unsigned) return unsigned
- mux (sel : std_logic;
s0 : signed;
s1 : signed) return signed