Entity: ddrio_in_xilinx

Diagram

positive BITS bit_vector INIT_VALUE std_logic Clock std_logic ClockEnable std_logic_vector(BITS - 1 downto 0) Pad std_logic_vector(BITS - 1 downto 0) DataIn_high std_logic_vector(BITS - 1 downto 0) DataIn_low

Description

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Authors: Martin Zabel Patrick Lehmann

Entity: Instantiates Chip-Specific DDR Input Registers for Xilinx FPGAs.

Description:

See PoC.io.ddrio.in for interface description.

License:

Copyright 2007-2015 Technische Universitaet Dresden - Germany, Chair of VLSI-Design, Diagnostics and Architecture

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and

limitations under the License.

Generics

Generic name Type Value Description
BITS positive
INIT_VALUE bit_vector x"FFFFFFFF"

Ports

Port name Direction Type Description
Clock in std_logic
ClockEnable in std_logic
DataIn_high out std_logic_vector(BITS - 1 downto 0)
DataIn_low out std_logic_vector(BITS - 1 downto 0)
Pad in std_logic_vector(BITS - 1 downto 0)