Entity: ddrio_out

File: ddrio_out.vhdl

Diagram

Description

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Authors: Martin Zabel Patrick Lehmann

Entity: Chip-Specific DDR Output Registers

Description:

Instantiates chip-specific :abbr:DDR (Double Data Rate) output registers.

Both data DataOut_high/low as well as OutputEnable are sampled with the rising_edge(Clock) from the on-chip logic. DataOut_high is brought out with this rising edge. DataOut_low is brought out with the falling edge.

OutputEnable (Tri-State) is high-active. It is automatically inverted if necessary. If an output enable is not required, you may save some logic by setting NO_OUTPUT_ENABLE = true.

If NO_OUTPUT_ENABLE = false then output is disabled after power-up. If NO_OUTPUT_ENABLE = true then output after power-up equals INIT_VALUE.

.. wavedrom::

Pad must be connected to a PAD because FPGAs only have these registers in IOBs.

License:

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and

limitations under the License.

Generics

Generic name	Type	Value
NO_OUTPUT_ENABLE	boolean	false
BITS	positive
INIT_VALUE	bit_vector	x"FFFFFFFF"

Ports

Port name	Direction	Type
Clock	in	std_logic
ClockEnable	in	std_logic
OutputEnable	in	std_logic
DataOut_high	in	std_logic_vector(BITS - 1 downto 0)
DataOut_low	in	std_logic_vector(BITS - 1 downto 0)
Pad	out	std_logic_vector(BITS - 1 downto 0)