Entity: filter_or
- File: filter_or.vhdl
Diagram
Description
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Authors: Patrick Lehmann
Entity: TODO
Description:
.. TODO:: No documentation available.
License:
Copyright 2007-2014 Technische Universitaet Dresden - Germany Chair of VLSI-Design, Diagnostics and Architecture
Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.
Generics
| Generic name | Type | Value | Description |
|---|---|---|---|
| TAPS | positive | 4 | |
| INIT | std_logic | '1' | |
| ADD_OUTPUT_REG | boolean | FALSE |
Ports
| Port name | Direction | Type | Description |
|---|---|---|---|
| Clock | in | std_logic | clock |
| DataIn | in | std_logic | data to filter |
| DataOut | out | std_logic | filtered signal |
Signals
| Name | Type | Description |
|---|---|---|
| Delays | std_logic_vector(TAPS - 1 downto 0) | |
| FilterOut | std_logic |