Entity: io_7SegmentMux_BCD

Diagram

FREQ CLOCK_FREQ FREQ REFRESH_RATE positive DIGITS std_logic Clock T_BCD_VECTOR(DIGITS - 1 downto 0) BCDDigits std_logic_vector(DIGITS - 1 downto 0) BCDDots std_logic_vector(7 downto 0) SegmentControl std_logic_vector(DIGITS - 1 downto 0) DigitControl

Description

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Authors: Patrick Lehmann

Entity: time multiplexed 7 Segment Display Controller for BCD chars

Description:

This module is a 7 segment display controller that uses time multiplexing to control a common anode for each digit in the display. The shown characters are BCD encoded. A dot per digit is optional. A minus sign for negative numbers is supported.

License:

Copyright 2007-2015 Technische Universitaet Dresden - Germany Chair of VLSI-Design, Diagnostics and Architecture

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and

limitations under the License.

Generics

Generic name Type Value Description
CLOCK_FREQ FREQ 100 MHz
REFRESH_RATE FREQ 1 kHz
DIGITS positive 4

Ports

Port name Direction Type Description
Clock in std_logic
BCDDigits in T_BCD_VECTOR(DIGITS - 1 downto 0)
BCDDots in std_logic_vector(DIGITS - 1 downto 0)
SegmentControl out std_logic_vector(7 downto 0)
DigitControl out std_logic_vector(DIGITS - 1 downto 0)

Signals

Name Type Description
DigitCounter_rst std_logic
DigitCounter_en std_logic
DigitCounter_us unsigned(log2ceilnz(DIGITS) - 1 downto 0)

Processes

Instantiations