Entity: lut_Sine

Diagram

boolean REG_OUTPUT positive MAX_AMPLITUDE positive POINTS REAL OFFSET_DEG positive QUARTERS std_logic Clock std_logic_vector(log2ceilnz(POINTS) - 1 downto 0) Input std_logic_vector(log2ceilnz(MAX_AMPLITUDE + ((QUARTERS - 1) / 2)) downto 0) Output

Description

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kate: tab-width 2; replace-tabs off; indent-width 2;

Authors: Patrick Lehmann

Entity: TODO

Description:

.. TODO:: No documentation available.

License:

Copyright 2007-2015 Technische Universitaet Dresden - Germany Chair of VLSI-Design, Diagnostics and Architecture

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and

limitations under the License.

Generics

Generic name Type Value Description
REG_OUTPUT boolean TRUE
MAX_AMPLITUDE positive 255
POINTS positive 4096
OFFSET_DEG REAL 0.0
QUARTERS positive 4

Ports

Port name Direction Type Description
Clock in std_logic
Input in std_logic_vector(log2ceilnz(POINTS) - 1 downto 0)
Output out std_logic_vector(log2ceilnz(MAX_AMPLITUDE + ((QUARTERS - 1) / 2)) downto 0)

Signals

Name Type Description
Output_nxt std_logic_vector(Output'range)