Entity: ocrom_dp

Diagram

positive A_BITS positive D_BITS string FILENAME std_logic clk1 std_logic clk2 std_logic ce1 std_logic ce2 unsigned(A_BITS-1 downto 0) a1 unsigned(A_BITS-1 downto 0) a2 std_logic_vector(D_BITS-1 downto 0) q1 std_logic_vector(D_BITS-1 downto 0) q2

Description

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Authors: Martin Zabel Patrick Lehmann

Entity: True dual-port memory.

Description:

Inferring / instantiating dual-port read-only memory, with:

  • dual clock, clock enable,
  • 2 read ports.

The generalized behavior across Altera and Xilinx FPGAs since Stratix/Cyclone and Spartan-3/Virtex-5, respectively, is as follows:

WARNING: The simulated behavior on RT-level is not correct.

TODO: add timing diagram TODO: implement correct behavior for RT-level simulation

License:

Copyright 2008-2015 Technische Universitaet Dresden - Germany Chair of VLSI-Design, Diagnostics and Architecture

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and

limitations under the License.

Generics

Generic name Type Value Description
A_BITS positive
D_BITS positive
FILENAME string ""

Ports

Port name Direction Type Description
clk1 in std_logic
clk2 in std_logic
ce1 in std_logic
ce2 in std_logic
a1 in unsigned(A_BITS-1 downto 0)
a2 in unsigned(A_BITS-1 downto 0)
q1 out std_logic_vector(D_BITS-1 downto 0)
q2 out std_logic_vector(D_BITS-1 downto 0)

Constants

Name Type Value Description
DEPTH positive 2**A_BITS