Entity: ocrom_sp

Diagram

positive A_BITS positive D_BITS string FILENAME std_logic clk std_logic ce unsigned(A_BITS-1 downto 0) a std_logic_vector(D_BITS-1 downto 0) q

Description

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Authors: Martin Zabel Patrick Lehmann

Entity: Single-port memory.

Description:

Inferring / instantiating single-port read-only memory

  • single clock, clock enable
  • 1 read port

License:

Copyright 2008-2015 Technische Universitaet Dresden - Germany Chair of VLSI-Design, Diagnostics and Architecture

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and

limitations under the License.

Generics

Generic name Type Value Description
A_BITS positive
D_BITS positive
FILENAME string ""

Ports

Port name Direction Type Description
clk in std_logic
ce in std_logic
a in unsigned(A_BITS-1 downto 0)
q out std_logic_vector(D_BITS-1 downto 0)

Constants

Name Type Value Description
DEPTH positive 2**A_BITS