Entity: pmod_USBUART

Diagram

FREQ CLOCK_FREQ BAUD BAUDRATE std_logic Clock std_logic Reset std_logic TX_put std_logic_vector(7 downto 0) TX_Data std_logic RX_got std_logic UART_RX std_logic UART_CTS std_logic TX_Full std_logic RX_Valid std_logic_vector(7 downto 0) RX_Data std_logic UART_TX std_logic UART_RTS

Description

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Authors: Patrick Lehmann

Entity: Digilent Peripherial Module: USB-UART (Pmod_USBUART)

Description:

This module abstracts a FTDI FT232R USB-UART bridge by instantiating a :doc:PoC.io.uart.fifo <../uart/uart_fifo>. The FT232R supports up to 3 MBaud. A synchronous FIFO interface with a 32 words buffer is provided. Hardware flow control (RTS_CTS) is enabled.

License:

Copyright 2007-2015 Technische Universitaet Dresden - Germany Chair of VLSI-Design, Diagnostics and Architecture

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

    http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and

limitations under the License.

Generics

Generic name Type Value Description
CLOCK_FREQ FREQ 100 MHz
BAUDRATE BAUD 115200 Bd

Ports

Port name Direction Type Description
Clock in std_logic
Reset in std_logic
TX_put in std_logic
TX_Data in std_logic_vector(7 downto 0)
TX_Full out std_logic
RX_Valid out std_logic
RX_Data out std_logic_vector(7 downto 0)
RX_got in std_logic
UART_TX out std_logic
UART_RX in std_logic
UART_RTS out std_logic
UART_CTS in std_logic

Instantiations